47 lines
957 B
C
47 lines
957 B
C
#include "shift_reg.h"
|
|
|
|
#include "ch32v003fun.h"
|
|
|
|
#define SRCLR (1 << 1)
|
|
#define SRCLK (1 << 2)
|
|
#define RCLK (1 << 3)
|
|
#define SER (1 << 4)
|
|
|
|
void shift_reg_init(void) {
|
|
RCC->APB2PCENR |= RCC_APB2Periph_GPIOC;
|
|
|
|
// PC1-PC4 as outputs
|
|
for (int pin = 1; pin <= 4; pin++) {
|
|
GPIOC->CFGLR &= ~(0xf << (4 * pin));
|
|
GPIOC->CFGLR |= (GPIO_Speed_10MHz | GPIO_CNF_OUT_PP) << (4 * pin);
|
|
}
|
|
|
|
GPIOC->BCR = SRCLR | SRCLK | RCLK | SER;
|
|
|
|
// reset shift register
|
|
GPIOC->BSHR = SRCLR;
|
|
GPIOC->BSHR = RCLK;
|
|
GPIOC->BCR = RCLK;
|
|
}
|
|
|
|
void shift_reg_write(uint16_t data) {
|
|
GPIOC->BCR = RCLK;
|
|
|
|
// reorder bits
|
|
uint16_t ordered_data = ((data & 0xFF00) >> 8) | ((data & 0x00FF) << 8);
|
|
|
|
// shift out 16 bits, MSB first
|
|
for (int8_t i = 15; i >= 0; i--) {
|
|
GPIOC->BCR = SRCLK;
|
|
if (ordered_data & (1 << i)) {
|
|
GPIOC->BSHR = SER;
|
|
} else {
|
|
GPIOC->BCR = SER;
|
|
}
|
|
GPIOC->BSHR = SRCLK;
|
|
}
|
|
|
|
GPIOC->BSHR = RCLK;
|
|
GPIOC->BCR = RCLK;
|
|
}
|