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.gitignore

@@ -3,3 +3,4 @@
 .vscode/c_cpp_properties.json
 .vscode/launch.json
 .vscode/ipch
+prv/

README.md

@@ -12,8 +12,8 @@ fw for a ch32v203 node w/ w5500 ethernet
   - SPI DMA only works with [prescalers](https://git.hye.su/mira/ch32-node/src/branch/master/src/spi_dma.c#L140) 8 and 64?
   - Also, for some reason it needs a ~50ms delay before configuring w5500 when compiled **with** `-O0`, not needed with `-Os`...
 
-idk...  
+Not an interrupt priority issue?:
-![systick_dma](notes/2024-10-14-182212_1566x610_scrot.png)
+![LA](notes/2024-10-15-001533_1895x722_scrot.png)
 
 
 ## ~~previous (DNS Processing)~~

src/funconfig.h

@@ -11,7 +11,7 @@
 #define FUNCONF_USE_UARTPRINTF 0
 #define FUNCONF_UART_PRINTF_BAUD \
   115200  // Only used if FUNCONF_USE_UARTPRINTF is set.
-#define FUNCONF_USE_CLK_SEC 0
+#define FUNCONF_USE_CLK_SEC 1
 #define FUNCONF_SYSTICK_USE_HCLK 1
 #define FUNCONF_DEBUG 1
 

src/gpio.c

@@ -6,8 +6,13 @@ void init_gpio(void) {
   // Enable clock for GPIOB
   RCC->APB2PCENR |= RCC_APB2Periph_GPIOB;
 
-  // GPIOB Configuration: Pins 3 and 4 as Output, Push-Pull, 10MHz
+  // GPIOB: Pins 3 and 4 as Output, Push-Pull, 10MHz
   GPIOB->CFGLR &= ~((0xF << (4 * 3)) | (0xF << (4 * 4)));
   GPIOB->CFGLR |= ((GPIO_Speed_10MHz | GPIO_CNF_OUT_PP) << (4 * 3)) |
                   ((GPIO_Speed_10MHz | GPIO_CNF_OUT_PP) << (4 * 4));
+
+  // XXX: SysTick debug
+  // GPIOB: Pin 9 as Output, Push-Pull, 10MHz
+  GPIOB->CFGHR &= ~(0xF << (4 * (9 - 8)));
+  GPIOB->CFGHR |= (GPIO_Speed_10MHz | GPIO_CNF_OUT_PP) << (4 * (9 - 8));
 }

src/main.c

@@ -14,6 +14,9 @@ void init_system(void) {
   SystemInit();
 
   init_gpio();
+  init_systick();
+  tim2_init();
+
   init_uart(UART_BRR_APB1);
   init_spidma();
 }
@@ -44,20 +47,33 @@ void message_arrived(MessageData* md) {
   }
 }
 
+void print_binary(uint32_t value) {
+  for (int i = 31; i >= 0; i--) {
+    DEBUG_PRINT("%d", (value >> i) & 1);
+    if (i % 4 == 0) printf(" ");  // Add space for readability
+  }
+  DEBUG_PRINT("\n");
+}
+
 int main(void) {
   init_system();
   Delay_Ms(55);
+
+  uint32_t intsyscr = __get_INTSYSCR();
+  DEBUG_PRINT("INTSYSCR Register Configuration:\n");
+  DEBUG_PRINT("Hexadecimal: 0x%08X\n", intsyscr);
+  DEBUG_PRINT("Binary: ");
+  print_binary(intsyscr);
+
   // DEBUG_PRINT("init_system() done\n");
   configure_network();
 
-  // TODO: enabling any kind of SysTick IRQ literally causes the socket to hang forever
+  // TODO: enabling any kind of SysTick IRQ literally causes the socket to hang
-  // with 1ms interval the hang is on DHCP_ACK, on check_DHCP_leasedIP -> sendto() ARP req
+  // forever with 1ms interval the hang is on DHCP_ACK, on check_DHCP_leasedIP
-  // with 1s it happens somewhere on DNS req
+  // -> sendto() ARP req with 100ms it happens somewhere on DNS req
-  // init_systick();
-  tim2_init();
 
-  // systick irq enable here would complete the DHCP configuration and hang on DNS..
+  // systick irq enable here would complete the DHCP configuration and hang on
-  // init_systick();
+  // DNS.. init_systick();
 
   configure_dhcp();
   resolve_domain_name("example.com");

src/spi_dma.c

@@ -118,7 +118,7 @@ void init_spidma(void) {
   // SPI1 Pin Configuration
   // CS on PA4, 10MHz Output, open-drain
   GPIOA->CFGLR &= ~(0xf << (4 * 4));
-  GPIOA->CFGLR |= (GPIO_Speed_10MHz | GPIO_CNF_OUT_OD) << (4 * 4);
+  GPIOA->CFGLR |= (GPIO_Speed_10MHz | GPIO_CNF_OUT_PP) << (4 * 4);
   // SCK on PA5, 10MHz Output, alt func, push-pull
   GPIOA->CFGLR &= ~(0xf << (4 * 5));
   GPIOA->CFGLR |= (GPIO_Speed_50MHz | GPIO_CNF_OUT_PP_AF) << (4 * 5);
@@ -159,8 +159,10 @@ void init_spidma(void) {
                         DMA_MemoryInc_Enable | DMA_PeripheralInc_Disable |
                         DMA_Mode_Normal | DMA_DIR_PeripheralSRC | DMA_IT_TC;
 
-  NVIC_SetPriority(DMA1_Channel2_IRQn, 0);
+  // NVIC_SetPriority(DMA1_Channel2_IRQn, 0);
-  NVIC_SetPriority(DMA1_Channel3_IRQn, 0);
+  // NVIC_SetPriority(DMA1_Channel3_IRQn, 0);
+  NVIC_SetPriority(DMA1_Channel2_IRQn, 0x20);
+  NVIC_SetPriority(DMA1_Channel3_IRQn, 0x20);
   NVIC_EnableIRQ(DMA1_Channel3_IRQn);
   NVIC_EnableIRQ(DMA1_Channel2_IRQn);
 }

src/systick.c

@@ -5,6 +5,7 @@
 
 // ms counter
 volatile uint32_t systick_millis = 0;
+volatile int toggle_state = 0;
 
 void init_systick(void) {
   SysTick->CTLR = 0;
@@ -13,7 +14,7 @@ void init_systick(void) {
   systick_millis = 0;
 
   // Enable the SysTick IRQ
-  NVIC_SetPriority(SysTicK_IRQn, 0xf0);
+  NVIC_SetPriority(SysTicK_IRQn, 0x60);
   NVIC_EnableIRQ(SysTicK_IRQn);
   /* Enable SysTick counter, IRQ, HCLK/1 */
   SysTick->CTLR = SYSTICK_CTLR_STE | SYSTICK_CTLR_STIE | SYSTICK_CTLR_STCLK;
@@ -26,6 +27,12 @@ void init_systick(void) {
  */
 void SysTick_Handler(void) __attribute__((interrupt));
 void SysTick_Handler(void) {
+  if (toggle_state) {
+    GPIOB->BSHR = (1 << 9);  // Set PB9 high
+  } else {
+    GPIOB->BCR = (1 << 9);  // Set PB9 low
+  }
+  toggle_state = !toggle_state;
   // Increment the Compare Register for the next trigger
   // If more than this number of ticks elapse before the trigger is reset,
   // you may miss your next interrupt trigger

src/timer.c

@@ -26,7 +26,7 @@ void tim2_init(void) {
   // Enable TIM2
   TIM2->CTLR1 |= TIM_CEN;
 
-//   NVIC_SetPriority(TIM2_IRQn, 0xf0);
+  NVIC_SetPriority(TIM2_IRQn, 0x40);
   NVIC_EnableIRQ(TIM2_IRQn);
 }