From 8f1700c09470d40a9cc2fba4881e4bca752774bc Mon Sep 17 00:00:00 2001 From: kuwoyuki Date: Thu, 10 Oct 2024 02:40:12 +0600 Subject: [PATCH] what --- README.md | 81 ++++++++++++++++++++++++++++++++++++++++++++++++++++++ src/main.c | 64 +++++++++++++++++++++++++++++++----------- 2 files changed, 129 insertions(+), 16 deletions(-) create mode 100644 README.md diff --git a/README.md b/README.md new file mode 100644 index 0000000..e6708f4 --- /dev/null +++ b/README.md @@ -0,0 +1,81 @@ +``` +Registering W5500 callbacks... +Calling wizchip_init()... +Calling DHCP_init()... +W5500 VERSIONR: 0x04 +Registering DHCP callbacks... +Calling DHCP_run()... +> Send DHCP_DISCOVER +DHCP message : 192.168.102.1(67) 311 received. +> Receive DHCP_OFFER +> Send DHCP_REQUEST +DHCP message : 192.168.102.1(67) 311 received. +> Receive DHCP_ACK + +> Check leased IP - OK +Callback: IP assigned! Leased time: 10 sec +IP: 192.168.102.113 +GW: 192.168.102.1 +Net: 255.255.255.0 +DNS: 192.168.102.1 +Calling wizchip_setnetinfo()... +Calling DNS_init()... +Resolving domain name "hye.su"... +> DNS Query to DNS Server : 192.168.102.1 +> Receive DNS message from 192.168.102.1(53). len = 21 +> Partial DNS message: 11 23 81 82 00 01 00 00 00 00 00 00 03 68 79 65 00 00 00 02 73 +DNS_run() failed, res = 0 +``` +w/ ch32v003fun +> Partial DNS message: `11 23 81 82 00 01 00 00 00 00 00 00 03 68 79 65 00 00 00 02 73` +**DNS_run() failed, res = 0** + +w/ WCH HAL (none-os).. I get a full response +> Receive DNS message from 192.168.102.1(53). len = 56 +> Partial DNS message: `11 23 81 80 00 01 00 02 00 00 00 00 03 68 79 65 02 73 75 00 00 01 00 01 C0 0C 00 01 00 01 00 00 01 2C 00 04 68 15 33 7F C0 0C 00 01 00 01 00 00 01 2C 00 04 AC 43 B4 9A ` +Result: 172.67.180.154 + +```c + // Initialize GPIO for W5500 CS + RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA, ENABLE); + GPIO_InitStructure.GPIO_Pin = W5500_CS_Pin; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_OD; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; + GPIO_Init(W5500_CS_GPIO_Port, &GPIO_InitStructure); + + // ... + static void MX_SPI1_Init(void) { + /* SPI1 parameter configuration*/ + GPIO_InitTypeDef GPIO_InitStructure = {0}; + SPI_InitTypeDef SPI_InitStructure = {0}; + + RCC_APB2PeriphClockCmd(RCC_APB2Periph_SPI1, ENABLE); + + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_5; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; + GPIO_Init(GPIOA, &GPIO_InitStructure); + + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_6; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING; + GPIO_Init(GPIOA, &GPIO_InitStructure); + + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_7; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; + GPIO_Init(GPIOA, &GPIO_InitStructure); + + SPI_InitStructure.SPI_Direction = SPI_Direction_2Lines_FullDuplex; + SPI_InitStructure.SPI_Mode = SPI_Mode_Master; + SPI_InitStructure.SPI_DataSize = SPI_DataSize_8b; + SPI_InitStructure.SPI_CPOL = SPI_CPOL_Low; // SPI Mode 0 (CPOL=0, CPHA=0) + SPI_InitStructure.SPI_CPHA = SPI_CPHA_1Edge; // SPI Mode 0 (CPOL=0, CPHA=0) + SPI_InitStructure.SPI_NSS = SPI_NSS_Soft; + SPI_InitStructure.SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_4; + SPI_InitStructure.SPI_FirstBit = SPI_FirstBit_MSB; + SPI_InitStructure.SPI_CRCPolynomial = 7; + SPI_Init(SPI1, &SPI_InitStructure); + + SPI_Cmd(SPI1, ENABLE); +} +``` \ No newline at end of file diff --git a/src/main.c b/src/main.c index ad9bc24..a5e38df 100644 --- a/src/main.c +++ b/src/main.c @@ -24,10 +24,6 @@ void init_system(void) { } void init_gpio(void) { - // PA4 (CS) - GPIOA->CFGLR &= ~(0xf << (4 * 4)); - GPIOA->CFGLR |= (GPIO_Speed_10MHz | GPIO_CNF_OUT_OD) << (4 * 4); - // GPIO PB3 pp GPIOB->CFGLR &= ~(0xf << (4 * 3)); GPIOB->CFGLR |= (GPIO_Speed_10MHz | GPIO_CNF_OUT_PP) << (4 * 3); @@ -41,27 +37,63 @@ void init_spi(void) { // Enable SPI1 RCC->APB2PCENR |= RCC_APB2Periph_SPI1; - // PA5 (SCK) alternate function, push-pull + // CS on PA4, 10MHz Output, open-drain + GPIOA->CFGLR &= ~(0xf << (4 * 4)); + GPIOA->CFGLR |= (GPIO_Speed_10MHz | GPIO_CNF_OUT_OD) << (4 * 4); + + // SCK on PA5, 10MHz Output, alt func, push-pull GPIOA->CFGLR &= ~(0xf << (4 * 5)); GPIOA->CFGLR |= (GPIO_Speed_50MHz | GPIO_CNF_OUT_PP_AF) << (4 * 5); - // PA6 (MISO) input, floating + + // MOSI on PA7, 10MHz input, floating GPIOA->CFGLR &= ~(0xf << (4 * 6)); GPIOA->CFGLR |= (GPIO_CNF_IN_FLOATING) << (4 * 6); - // PA7 (MOSI) alternate function, push-pull + + // MISO on PA6, 10MHz Output, alt func, push-pull GPIOA->CFGLR &= ~(0xf << (4 * 7)); GPIOA->CFGLR |= (GPIO_Speed_50MHz | GPIO_CNF_OUT_PP_AF) << (4 * 7); - SPI1->CTLR1 = SPI_Direction_2Lines_FullDuplex | SPI_Mode_Master | - SPI_DataSize_8b | SPI_CPOL_High | SPI_CPHA_2Edge | SPI_NSS_Soft | - SPI_BaudRatePrescaler_4 | SPI_FirstBit_MSB; + // SPI1->CTLR1 = (0 << 15) | // BIDIMODE + // (0 << 14) | // BIDIOE + // (0 << 13) | // CRCEN + // (0 << 12) | // CRCNEXT + // (0 << 11) | // DFF + // (0 << 10) | // RXONLY + // (1 << 9) | // SSM + // (0 << 8) | // SSI + // (0 << 7) | // LSBFIRST + // (0 << 6) | // SPE (Enable SPI) + // (1 << 5) | // BR[2] (Set baud rate) + // (0 << 4) | // BR[1] + // (0 << 3) | // BR[0] + // (1 << 2) | // MSTR (Master mode) + // (0 << 1) | // CPOL + // (0); // CPHA - SPI1->I2SCFGR &= SPI_Mode_Select; // Disable I2S mode - // SPI1->CRCR = 7; // 8-bit CRC polynomial - // SPI1->CTLR1 &= ~(SPI_CTLR1_DFF); // 8-bit data frame - SPI1->CTLR1 |= CTLR1_SPE_Set; + // reset control register + SPI1->CTLR1 = 0; - // CS high initially - GPIOA->BSHR = (1 << 4); + // set prescaler + // 001: FPCLK/4; + SPI1->CTLR1 = (SPI1->CTLR1 & ~SPI_CTLR1_BR) | (0x1 << 3); + + // set clock polarity and phase + SPI1->CTLR1 |= (SPI_CPOL_Low | SPI_CPHA_1Edge); + + // configure NSS pin, master mode + SPI1->CTLR1 |= SPI_NSS_Soft; // SSM NSS software control mode + + // CH32V203 is master + SPI1->CTLR1 |= SPI_Mode_Master; + + // set data direction and configure data pins + SPI1->CTLR1 |= SPI_Direction_2Lines_FullDuplex; + + // disable I2S mode + SPI1->I2SCFGR &= SPI_Mode_Select; + SPI1->CTLR1 &= ~(SPI_CTLR1_DFF); // DFF 16bit data-length enable, writable + // only when SPE is 0 + SPI1->CTLR1 |= SPI_CTLR1_SPE; } volatile int ip_assigned = 0;