kuwoyuki
8adc726b0b
Squashed commit of the following: commit 5f16309f629b9928d2134b85ae64af69bc3ebbcd Author: kuwoyuki <kuwoyuki@cock.li> Date: Sun Nov 24 22:55:15 2024 +0600 fix: Makefile, improve onewire retries commit 55496a3bda941b52ff349dc75c9c06eb5a37c07d Author: kuwoyuki <kuwoyuki@cock.li> Date: Mon Nov 18 00:41:18 2024 +0600 fix: make onewire validity less strict commit 3428a9bc9792508972ce3e7e4e35a64f047bca10 Author: kuwoyuki <kuwoyuki@cock.li> Date: Sun Nov 17 23:57:55 2024 +0600 chore: rm bins commit 1594e5ed430522b15466c8afa62ff7fb1b28947c Author: kuwoyuki <kuwoyuki@cock.li> Date: Sun Nov 17 23:32:01 2024 +0600 chore: unplatformiofy
95 lines
3.1 KiB
C
95 lines
3.1 KiB
C
#include "uart.h"
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#include "ch32v003fun.h"
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#define RS485_TX_EN (1 << 14) // PB14
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#define RS485_RX_EN (1 << 15) // PB15
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// Write multiple chars to UART
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int _write(__attribute__((unused)) int fd, const char *buf, int size) {
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for (int i = 0; i < size; i++) {
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while (!(USART2->STATR & USART_FLAG_TC)); // Wait for transmission complete
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USART2->DATAR = *buf++; // Send character
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}
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return size;
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}
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// Write a single char to UART
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int putchar(int c) {
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while (!(USART2->STATR & USART_FLAG_TC)); // Wait for transmission complete
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USART2->DATAR = (uint8_t)c; // Send character
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return (unsigned char)c;
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}
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void uart2_init(int uart_brr) {
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RCC->APB2PCENR |= RCC_APB2Periph_GPIOA; // Enable GPIOA on APB2
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RCC->APB1PCENR |= RCC_APB1Periph_USART2; // Enable USART2 on APB1
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GPIOA->CFGLR &= ~(0xf << (4 * 2)); // Clear bits for PA2
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GPIOA->CFGLR |= (GPIO_Speed_10MHz | GPIO_CNF_OUT_PP_AF)
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<< (4 * 2); // Set PA2 as AF
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// USART configuration: 115200 baud rate, 8 data bits, no parity, 1 stop bit
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USART2->CTLR1 = USART_WordLength_8b | USART_Parity_No | USART_Mode_Tx;
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USART2->CTLR2 = USART_StopBits_1;
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USART2->CTLR3 = USART_HardwareFlowControl_None;
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USART2->BRR = uart_brr;
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// Enable USART2
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USART2->CTLR1 |= CTLR1_UE_Set;
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}
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void rs485_init(int uart_brr) {
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RCC->APB2PCENR |= RCC_APB2Periph_GPIOA | // Enable GPIOA
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RCC_APB2Periph_GPIOB | // Enable GPIOB
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RCC_APB2Periph_USART1; // Enable USART1
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// configure uart1 pins (PA9=TX, PA10=RX)
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GPIOA->CFGHR &=
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~(0xf << (4 * 1) | 0xf << (4 * 2)); // Clear PA9 & PA10 config
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GPIOA->CFGHR |= (GPIO_Speed_10MHz | GPIO_CNF_OUT_PP_AF)
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<< (4 * 1); // PA9 (TX)
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GPIOA->CFGHR |= GPIO_CNF_IN_FLOATING << (4 * 2); // PA10 (RX)
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// configure rs485 direction control pins (PB14=TX_EN, PB15=RX_EN)
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GPIOB->CFGHR &=
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~(0xf << (4 * 6) | 0xf << (4 * 7)); // Clear PB14 & PB15 config
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GPIOB->CFGHR |= (GPIO_Speed_10MHz | GPIO_CNF_OUT_PP)
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<< (4 * 6); // PB14 (TX_EN)
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GPIOB->CFGHR |= (GPIO_Speed_10MHz | GPIO_CNF_OUT_PP)
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<< (4 * 7); // PB15 (RX_EN)
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// initial state: rx mode
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GPIOB->BCR = RS485_TX_EN; // TX_EN low
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GPIOB->BSHR = RS485_RX_EN; // RX_EN high
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// uart1 configuration
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USART1->CTLR1 =
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USART_WordLength_8b | USART_Parity_No | USART_Mode_Tx | USART_Mode_Rx;
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USART1->CTLR2 = USART_StopBits_1;
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USART1->CTLR3 = USART_HardwareFlowControl_None;
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USART1->BRR = uart_brr;
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USART1->CTLR1 |= CTLR1_UE_Set;
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}
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void rs485_send(uint8_t *buf, uint16_t len) {
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// enable tx mode
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GPIOB->BSHR = RS485_TX_EN; // TX_EN high
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GPIOB->BSHR = RS485_RX_EN; // RX_EN low
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for (uint16_t i = 0; i < len; i++) {
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while (!(USART1->STATR & USART_FLAG_TXE));
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USART1->DATAR = buf[i];
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}
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while (!(USART1->STATR & USART_FLAG_TC));
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// switch back to rx mode
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GPIOB->BCR = RS485_TX_EN; // TX_EN low
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GPIOB->BCR = RS485_RX_EN; // RX_EN high
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}
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uint8_t rs485_available(void) { return (USART1->STATR & USART_FLAG_RXNE) != 0; }
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uint8_t rs485_read(void) { return USART1->DATAR & 0xFF; }
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