mira/ch32v208_sens
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120mhz clock

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Mira
2025-11-10 02:55:12 +06:00
parent 7877bb42f4
commit 6e29b34542
1 changed files with 40 additions and 35 deletions
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75
main.c
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@@ -33,41 +33,51 @@ int clock_init(void);
void led_init(void); void led_init(void);
void lwip_stack_init(void); void lwip_stack_init(void);
int clock_init(void) { static void set_sysclk_to_120mhz_from_hse(void) {
RCC->INTR = 0x009f0000; volatile uint32_t startup_counter = 0;
RCC->CTLR &= ~(RCC_HSE_ON | RCC_PLLON);
RCC->CFGR0 = 0x00000000;
RCC->CTLR |= RCC_HSE_ON; RCC->CTLR |= RCC_HSEON;
for (int timeout = HSE_STARTUP_TIMEOUT; timeout > 0; timeout--) {
if (RCC->CTLR & RCC_HSERDY) break; do {
if (timeout == 1) { startup_counter++;
printf("Error: HSE failed to start\n"); } while (!(RCC->CTLR & RCC_HSERDY) &&
return -1; (startup_counter < HSE_STARTUP_TIMEOUT));
if (RCC->CTLR & RCC_HSERDY) {
/*
* HCLK (AHB) = SYSCLK / 2
* PCLK2 (APB2) = HCLK / 1
* PCLK1 (APB1) = HCLK / 2
* USB Clock = PLLCLK / 5 (to get 48MHz for USB)
*/
RCC->CFGR0 |=
RCC_HPRE_DIV2 | RCC_PPRE2_DIV1 | RCC_PPRE1_DIV2 | RCC_USBPRE_DIV5;
/*
* When RCC_USBPRE is 3 it changes HPE div to /2 instead of /4, so:
* PLL Source: HSE
* HSE Divider for PLL: /2
* PLL Multiplier: x15
* PLL Clock = (32MHz / 2) * 15 = 240 MHz
*/
uint32_t pll_config = RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL15;
RCC->CFGR0 =
(RCC->CFGR0 & ~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL)) | pll_config;
RCC->CTLR |= RCC_PLLON;
// wait for pll to lock
while (!(RCC->CTLR & RCC_PLLRDY)) {
} }
}
RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2; // PLL as the system clock src
RCC->CFGR2 = (PREDIV1_DIVISOR - 1); RCC->CFGR0 = (RCC->CFGR0 & ~RCC_SW) | RCC_SW_PLL;
RCC->CFGR0 |= RCC_PLLSource_HSE_Div1 | RCC_PLLMul_15;
RCC->CTLR |= RCC_PLLON; while ((RCC->CFGR0 & RCC_SWS) != RCC_SWS_PLL) {
printf("Main PLL en. Waiting for lock...\n");
for (int timeout = PLL_LOCK_TIMEOUT; timeout > 0; timeout--) {
if (RCC->CTLR & RCC_PLLRDY) break;
if (timeout == 1) {
printf("Error: Main PLL lock failed\n");
return -1;
} }
} else {
printf("HSE failed to start\n");
} }
printf("Main PLL Locked\n");
RCC->CFGR0 = (RCC->CFGR0 & ~RCC_SW) | RCC_SW_PLL;
while ((RCC->CFGR0 & RCC_SWS) != RCC_SWS_PLL);
printf("System clock set to %dMHz.\n",
(HSE_CLOCK_MHZ / PREDIV1_DIVISOR) * PLL_MULTIPLIER);
return 0;
} }
void led_init(void) { void led_init(void) {
@@ -159,12 +169,7 @@ void ethernetif_print_stats(void) {
int main() { int main() {
SystemInit(); SystemInit();
set_sysclk_to_120mhz_from_hse();
if (clock_init() != 0) {
// eating dirt?
while (1);
}
systick_init(); systick_init();
led_init(); led_init();
lwip_stack_init(); lwip_stack_init();