mira/ch32v208_sens
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clean up? idk

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Mira
2025-11-08 18:00:46 +06:00
parent 686bccd0ce
commit aa367e5a24
6 changed files with 181 additions and 265 deletions
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176
port/ethernetif.c
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@@ -15,7 +15,6 @@
#define ETH_RXBUFNB 4
#define ETH_TXBUFNB 1
#define ETH_MAX_PACKET_SIZE 1520
#define ETH_RX_BUF_SZE ETH_MAX_PACKET_SIZE
#define ETH_TX_BUF_SZE ETH_MAX_PACKET_SIZE
@@ -30,6 +29,7 @@ __attribute__((aligned(4))) uint8_t MACRxBuf[ETH_RXBUFNB * ETH_RX_BUF_SZE];
__attribute__((aligned(4))) uint8_t MACTxBuf[ETH_TXBUFNB * ETH_TX_BUF_SZE];
static volatile bool g_link_interrupt_flag = false;
static struct ethernetif eth_state;
static void low_level_init(struct netif* netif);
static err_t low_level_output(struct netif* netif, struct pbuf* p);
@@ -46,17 +46,11 @@ static void eth_get_mac_in_uc(uint8_t* mac) {
}
err_t ethernetif_init(struct netif* netif) {
struct ethernetif* ethernetif = mem_malloc(sizeof(struct ethernetif));
if (ethernetif == NULL) {
LWIP_DEBUGF(NETIF_DEBUG, ("ethernetif_init: out of memory\n"));
return ERR_MEM;
}
#if LWIP_NETIF_HOSTNAME
netif->hostname = "lwip-ch32";
#endif
netif->state = ethernetif;
netif->state = &eth_state;
netif->name[0] = IFNAME0;
netif->name[1] = IFNAME1;
@@ -66,19 +60,11 @@ err_t ethernetif_init(struct netif* netif) {
MIB2_INIT_NETIF(netif, snmp_ifType_ethernet_csmacd, 10000000); // 10Mbps
netif->hwaddr_len = ETH_HWADDR_LEN;
uint8_t mac_addr[6];
eth_get_mac_in_uc(mac_addr);
eth_get_mac_in_uc(netif->hwaddr);
printf("MAC Address: %02X:%02X:%02X:%02X:%02X:%02X\n", mac_addr[0],
mac_addr[1], mac_addr[2], mac_addr[3], mac_addr[4], mac_addr[5]);
/* set MAC hardware address */
netif->hwaddr[0] = mac_addr[0];
netif->hwaddr[1] = mac_addr[1];
netif->hwaddr[2] = mac_addr[2];
netif->hwaddr[3] = mac_addr[3];
netif->hwaddr[4] = mac_addr[4];
netif->hwaddr[5] = mac_addr[5];
printf("MAC Address: %02X:%02X:%02X:%02X:%02X:%02X\n", netif->hwaddr[0],
netif->hwaddr[1], netif->hwaddr[2], netif->hwaddr[3], netif->hwaddr[4],
netif->hwaddr[5]);
netif->mtu = 1500;
netif->flags = NETIF_FLAG_BROADCAST | NETIF_FLAG_ETHARP;
@@ -93,15 +79,15 @@ static void low_level_init(struct netif* netif) {
// clocks
RCC->APB2PCENR |= RCC_APB2Periph_AFIO;
RCC->CFGR0 = (RCC->CFGR0 & ~((uint32_t)1 << 28)) | (RCC_ETHCLK_Div2 << 28);
RCC->CFGR0 |= RCC_ETHPRE; // div 2
EXTEN->EXTEN_CTR |= EXTEN_ETH_10M_EN;
// mac reset
ETH10M->ECON1 |= (RB_ETH_ECON1_TXRST | RB_ETH_ECON1_RXRST);
ETH10M->ECON1 &= ~(RB_ETH_ECON1_TXRST | RB_ETH_ECON1_RXRST);
// reset mac rx and tx
ETH10M->ECON1 = RB_ETH_ECON1_TXRST | RB_ETH_ECON1_RXRST;
ETH10M->ECON1 = 0;
// mac regs
ETH10M->ERXFON = RB_ETH_ERXFCON_BCEN | RB_ETH_ERXFCON_MCEN;
ETH10M->ERXFCON = RB_ETH_ERXFCON_BCEN | RB_ETH_ERXFCON_MCEN;
ETH10M->MACON1 = RB_ETH_MACON1_MARXEN;
ETH10M->MACON2 = PADCFG_AUTO_3 | RB_ETH_MACON2_TXCRCEN;
ETH10M->MAMXFL = ETH_MAX_PACKET_SIZE;
@@ -114,43 +100,56 @@ static void low_level_init(struct netif* netif) {
R8_ETH_MAADRL6 = netif->hwaddr[0];
// PHY analog block
ETH10M->ECON2 = (ETH10M->ECON2 & ~(0x07 << 1)) | (5 << 1);
ETH10M->ECON2 = RB_ETH_ECON2_DEFAULT;
// DMA descriptors
ethernetif->DMATxDescToSet = &DMATxDscrTab[0];
DMATxDscrTab[0].Status = 0;
DMATxDscrTab[0].Buffer1Addr = (uint32_t)MACTxBuf;
DMATxDscrTab[0].Buffer2NextDescAddr = (uint32_t)&DMATxDscrTab[0];
ethernetif->DMARxDescToGet = &DMARxDscrTab[0];
for (int i = 0; i < ETH_RXBUFNB; i++) {
DMARxDscrTab[i].Status = 0;
DMARxDscrTab[i].Buffer1Addr = (uint32_t)(&MACRxBuf[i * ETH_RX_BUF_SZE]);
DMARxDscrTab[i].Buffer2NextDescAddr =
(uint32_t)(&DMARxDscrTab[(i + 1) % ETH_RXBUFNB]);
// init TX descriptors
ethernetif->DMATxDescToSet = DMATxDscrTab;
for (int i = 0; i < ETH_TXBUFNB; i++) {
DMATxDscrTab[i].Status = 0;
DMATxDscrTab[i].Buffer1Addr = (uint32_t)&MACTxBuf[i * ETH_TX_BUF_SZE];
DMATxDscrTab[i].Buffer2NextDescAddr =
(uint32_t)&DMATxDscrTab[(i + 1) % ETH_TXBUFNB];
}
ETH10M->ERXST = (uint32_t)ethernetif->DMARxDescToGet->Buffer1Addr;
ETH10M->ECON1 |= RB_ETH_ECON1_RXEN;
// init RX descriptors
ethernetif->DMARxDescToGet = DMARxDscrTab;
for (int i = 0; i < ETH_RXBUFNB; i++) {
DMARxDscrTab[i].Status = 0;
DMARxDscrTab[i].Buffer1Addr = (uint32_t)&MACRxBuf[i * ETH_RX_BUF_SZE];
DMARxDscrTab[i].Buffer2NextDescAddr =
(uint32_t)&DMARxDscrTab[(i + 1) % ETH_RXBUFNB];
}
// set RX buffer start and enable receiver
ETH10M->ERXST = ethernetif->DMARxDescToGet->Buffer1Addr;
ETH10M->ECON1 = RB_ETH_ECON1_RXEN;
printf("Resetting PHY...\n");
WritePHYReg(PHY_BMCR, PHY_BMCR_RESET);
Delay_Ms(200);
printf("Starting PHY, Mode: 10BASE_T_FD\n");
WritePHYReg(PHY_BMCR, PHY_BMCR_FORCE_10BASE_T_FD);
WritePHYReg(PHY_BMCR, PHY_BMCR_FULL_DUPLEX);
ETH10M->EIR = 0xFF; // clear all interrupt flags
ETH10M->EIE = RB_ETH_EIE_INTIE | RB_ETH_EIE_TXIE | RB_ETH_EIE_LINKIE |
RB_ETH_EIE_TXERIE | RB_ETH_EIE_RXERIE | RB_ETH_EIE_R_EN50;
ETH10M->EIE = RB_ETH_EIE_INTIE | RB_ETH_EIE_TXIE | RB_ETH_EIE_LINKIE;
ETH10M->EIR = 0xFF;
NVIC_EnableIRQ(ETH_IRQn);
printf("low_level_init: done\n");
}
static err_t low_level_output(struct netif* netif, struct pbuf* p) {
if (DMATxDscrTab[0].Status & ETH_DMATxDesc_OWN) return ERR_BUF;
if (DMATxDscrTab[0].Status & ETH_DMATxDesc_OWN) {
#if LWIP_STATS
LINK_STATS_INC(link.drop);
#endif
return ERR_BUF;
}
uint32_t len = 0;
uint8_t* tx_buf_ptr = (uint8_t*)DMATxDscrTab[0].Buffer1Addr;
for (struct pbuf* q = p; q != NULL; q = q->next) {
memcpy(&tx_buf_ptr[len], q->payload, q->len);
len += q->len;
@@ -161,41 +160,61 @@ static err_t low_level_output(struct netif* netif, struct pbuf* p) {
DMATxDscrTab[0].Status |= ETH_DMATxDesc_OWN;
ETH10M->ECON1 |= RB_ETH_ECON1_TXRTS;
#if LWIP_STATS
LINK_STATS_INC(link.xmit);
#endif
MIB2_STATS_NETIF_ADD(netif, ifoutoctets, len);
return ERR_OK;
}
static struct pbuf* low_level_input(struct netif* netif) {
struct ethernetif* ethernetif = netif->state;
uint16_t len;
uint8_t* current_rx_buffer_ptr;
if ((ETH10M->EIR & RB_ETH_EIR_RXIF) == 0) return NULL;
if (!(ETH10M->EIR & RB_ETH_EIR_RXIF)) {
return NULL;
}
len = ETH10M->ERXLN;
current_rx_buffer_ptr = (uint8_t*)ethernetif->DMARxDescToGet->Buffer1Addr;
uint16_t len = ETH10M->ERXLN;
if (len < MIN_ETH_FRAME_SIZE || len > ETH_MAX_PACKET_SIZE) {
#if LWIP_STATS
LINK_STATS_INC(link.lenerr);
#endif
ETH10M->EIR = RB_ETH_EIR_RXIF;
ETH10M->ECON1 |= RB_ETH_ECON1_RXEN;
return NULL;
}
uint8_t* current_rx_buffer_ptr =
(uint8_t*)ethernetif->DMARxDescToGet->Buffer1Addr;
struct pbuf* p = pbuf_alloc(PBUF_RAW, len, PBUF_POOL);
if (p != NULL) {
uint32_t offset = 0;
for (struct pbuf* q = p; q != NULL; q = q->next) {
memcpy(q->payload, current_rx_buffer_ptr + offset, q->len);
offset += q->len;
}
#if LWIP_STATS
LINK_STATS_INC(link.recv);
#endif
MIB2_STATS_NETIF_ADD(netif, ifinoctets, len);
} else {
#if LWIP_STATS
LINK_STATS_INC(link.memerr);
LINK_STATS_INC(link.drop);
#endif
MIB2_STATS_NETIF_INC(netif, ifindiscards);
}
// move to next descriptor
ethernetif->DMARxDescToGet =
(ETH_DMADESCTypeDef*)ethernetif->DMARxDescToGet->Buffer2NextDescAddr;
ETH10M->ERXST = (uint32_t)ethernetif->DMARxDescToGet->Buffer1Addr;
ETH10M->EIR = RB_ETH_EIR_RXIF;
ETH10M->ECON1 |= RB_ETH_ECON1_RXEN;
struct pbuf* p = NULL;
if (len > 0) {
p = pbuf_alloc(PBUF_RAW, len, PBUF_POOL);
if (p != NULL) {
uint32_t bytes_copied = 0;
for (struct pbuf* q = p; q != NULL; q = q->next) {
memcpy(q->payload, current_rx_buffer_ptr + bytes_copied, q->len);
bytes_copied += q->len;
}
MIB2_STATS_NETIF_ADD(netif, ifinoctets, len);
} else {
MIB2_STATS_NETIF_INC(netif, ifindiscards);
}
}
ETH10M->EIR = RB_ETH_EIR_RXIF;
return p;
}
@@ -209,11 +228,11 @@ void ethernetif_input(struct netif* netif) {
}
void ethernetif_link_poll(struct netif* netif) {
if (!g_link_interrupt_flag) {
return;
}
if (!g_link_interrupt_flag) return;
g_link_interrupt_flag = false;
// supposedly, first read latches link status 2nd get cur val
(void)ReadPHYReg(PHY_BMSR);
uint16_t bmsr = ReadPHYReg(PHY_BMSR);
if (bmsr & PHY_BMSR_LINK_STATUS) {
@@ -230,7 +249,7 @@ void ethernetif_link_poll(struct netif* netif) {
}
}
void ETH_IRQHandler(void) __attribute__((interrupt));
void ETH_IRQHandler(void) __attribute__((interrupt)) __attribute__((used));
void ETH_IRQHandler(void) {
uint32_t flags = ETH10M->EIR;
@@ -239,6 +258,22 @@ void ETH_IRQHandler(void) {
ETH10M->EIR = RB_ETH_EIR_TXIF;
}
if (flags & RB_ETH_EIR_TXERIF) {
DMATxDscrTab[0].Status &= ~ETH_DMATxDesc_OWN;
ETH10M->EIR = RB_ETH_EIR_TXERIF;
#if LWIP_STATS
LINK_STATS_INC(link.err);
#endif
}
if (flags & RB_ETH_EIR_RXERIF) {
ETH10M->EIR = RB_ETH_EIR_RXERIF;
ETH10M->ECON1 |= RB_ETH_ECON1_RXEN;
#if LWIP_STATS
LINK_STATS_INC(link.err);
#endif
}
if (flags & RB_ETH_EIR_LINKIF) {
g_link_interrupt_flag = true;
ETH10M->EIR = RB_ETH_EIR_LINKIF;
@@ -246,7 +281,8 @@ void ETH_IRQHandler(void) {
}
void WritePHYReg(uint8_t reg_add, uint16_t reg_val) {
R32_ETH_MIWR = (reg_add & RB_ETH_MIREGADR_MIRDL) | (1 << 8) | (reg_val << 16);
R32_ETH_MIWR = (reg_add & RB_ETH_MIREGADR_MASK) | RB_ETH_MIWR_MIIWR |
RB_ETH_MIWR_DATA_SHIFT;
}
uint16_t ReadPHYReg(uint8_t reg_add) {