From e448282aedd0fb08eb78241e3cbb03a93f8d17ee Mon Sep 17 00:00:00 2001
From: kuwoyuki <kuwoyuki@cock.li>
Date: Mon, 10 Nov 2025 12:00:21 +0600
Subject: [PATCH] fix: correctly deinit rcc before hse sw

---
 funconfig.h |  4 ++--
 main.c      | 12 ++++++++++--
 2 files changed, 12 insertions(+), 4 deletions(-)

diff --git a/funconfig.h b/funconfig.h
index 1685965..4382498 100644
--- a/funconfig.h
+++ b/funconfig.h
@@ -1,9 +1,9 @@
 #ifndef _FUNCONFIG_H
 #define _FUNCONFIG_H
 
-#define FUNCONF_USE_HSE 1
+// #define FUNCONF_USE_HSE 1
 #define FUNCONF_SYSTEM_CORE_CLOCK 120000000
-#define FUNCONF_PLL_MULTIPLIER 15
+// #define FUNCONF_PLL_MULTIPLIER 15
 #define FUNCONF_SYSTICK_USE_HCLK 1
 
 #endif
diff --git a/main.c b/main.c
index 5ab015d..ad42f19 100644
--- a/main.c
+++ b/main.c
@@ -29,13 +29,21 @@
 struct netif g_netif;
 static volatile int g_httpd_is_initialized = 0;
 
-int clock_init(void);
 void led_init(void);
 void lwip_stack_init(void);
 
 static void set_sysclk_to_120mhz_from_hse(void) {
-  volatile uint32_t startup_counter = 0;
+  uint32_t startup_counter = 0;
 
+  RCC->INTR = 0x009F0000;  // clear PLL, CSSC, HSE, HSI and LSI ready flags.
+  // switch processor back to HSI so we don't eat dirt.
+  RCC->CFGR0 = 0;
+  // disable PLL so we can play with it.
+  RCC->CTLR &= ~RCC_PLLON;
+  // not sure why, need to reset here, otherwise PLLXTPRE is set.
+  RCC->CFGR0 = RCC_PLLSRC;
+
+  // enable HSE
   RCC->CTLR |= RCC_HSEON;
 
   do {