#ifndef __ETHERNETIF_H #define __ETHERNETIF_H #include "lwip/err.h" #include "lwip/netif.h" void run_tx_test(void); void WritePHYReg(uint8_t reg_add, uint16_t reg_val); uint16_t ReadPHYReg(uint8_t reg_add); #define ROM_CFG_USERADR_ID 0x1FFFF7E8 #define PHY_BMCR_FORCE_10BASE_T_HD ((uint16_t)0x0000) #define PHY_BMCR_FORCE_10BASE_T_FD ((uint16_t)0x0100) // 10M, Full Duplex #define PHY_ANAR_SELECTOR_FIELD 0x0001 // Selector for 802.3 #define PHY_ANAR_10BASET_HD 0x0020 // 10M Half-Duplex #define PHY_ANAR_10BASET_FD 0x0040 // 10M Full-Duplex #define PHY_PHYSR 0x10 // PHY Status Register // Bits for CH32V20x PHYSR #define PHY_PHYSR_FULL_10M (1 << 2) #define PHY_BMCR_RESET ((uint16_t)0x8000) // Reset PHY #define PHY_BMCR_AN_ENABLE \ ((uint16_t)0x1000) // Enable Auto-Negotiation (Bit 12) #define PHY_BMCR_AN_RESTART \ ((uint16_t)0x0200) // Restart Auto-Negotiation (Bit 9) #define PHY_BMSR_LINK_STATUS (1 << 2) #define PHY_BMSR_AN_COMPLETE (1 << 5) #define PHY_MDIX_PN_MASK (3 << 2) // Mask for bits [3:2] -> 0x0C #define PHY_MDIX_PN_REVERSED \ (1 << 2) // Value for reversed polarity (01b) -> 0x04 /** DMA Tx Desciptor ----------------------------------------------------------------------------------------------- TDES0 | OWN(31) | CTRL[30:26] | Reserved[25:24] | CTRL[23:20] | Reserved[19:17] | Status[16:0] | ----------------------------------------------------------------------------------------------- TDES1 | Reserved[31:29] | Buffer2 ByteCount[28:16] | Reserved[15:13] | Buffer1 ByteCount[12:0] | ----------------------------------------------------------------------------------------------- TDES2 | Buffer1 Address [31:0] | ----------------------------------------------------------------------------------------------- TDES3 | Buffer2 Address [31:0] / Next Desciptor Address [31:0] | ------------------------------------------------------------------------------------------------ */ /* Bit or field definition of TDES0 register (DMA Tx descriptor status * register)*/ #define ETH_DMATxDesc_OWN \ ((uint32_t)0x80000000) /* OWN bit: descriptor is owned by DMA engine */ #define ETH_DMATxDesc_IC ((uint32_t)0x40000000) /* Interrupt on Completion */ #define ETH_DMATxDesc_LS ((uint32_t)0x20000000) /* Last Segment */ #define ETH_DMATxDesc_FS ((uint32_t)0x10000000) /* First Segment */ #define ETH_DMATxDesc_DC ((uint32_t)0x08000000) /* Disable CRC */ #define ETH_DMATxDesc_DP ((uint32_t)0x04000000) /* Disable Padding */ #define ETH_DMATxDesc_TTSE \ ((uint32_t)0x02000000) /* Transmit Time Stamp Enable */ #define ETH_DMATxDesc_CIC \ ((uint32_t)0x00C00000) /* Checksum Insertion Control: 4 cases */ #define ETH_DMATxDesc_CIC_ByPass \ ((uint32_t)0x00000000) /* Do Nothing: Checksum Engine is bypassed */ #define ETH_DMATxDesc_CIC_IPV4Header \ ((uint32_t)0x00400000) /* IPV4 header Checksum Insertion */ #define ETH_DMATxDesc_CIC_TCPUDPICMP_Segment \ ((uint32_t)0x00800000) /* TCP/UDP/ICMP Checksum Insertion calculated over \ segment only */ #define ETH_DMATxDesc_CIC_TCPUDPICMP_Full \ ((uint32_t)0x00C00000) /* TCP/UDP/ICMP Checksum Insertion fully calculated \ */ #define ETH_DMATxDesc_TER ((uint32_t)0x00200000) /* Transmit End of Ring */ #define ETH_DMATxDesc_TCH ((uint32_t)0x00100000) /* Second Address Chained */ #define ETH_DMATxDesc_TTSS ((uint32_t)0x00020000) /* Tx Time Stamp Status */ #define ETH_DMATxDesc_IHE ((uint32_t)0x00010000) /* IP Header Error */ #define ETH_DMATxDesc_ES \ ((uint32_t)0x00008000) /* Error summary: OR of the following bits: UE || ED \ || EC || LCO || NC || LCA || FF || JT */ #define ETH_DMATxDesc_JT ((uint32_t)0x00004000) /* Jabber Timeout */ #define ETH_DMATxDesc_FF \ ((uint32_t)0x00002000) /* Frame Flushed: DMA/MTL flushed the frame due to SW \ flush */ #define ETH_DMATxDesc_PCE ((uint32_t)0x00001000) /* Payload Checksum Error */ #define ETH_DMATxDesc_LCA \ ((uint32_t)0x00000800) /* Loss of Carrier: carrier lost during tramsmission \ */ #define ETH_DMATxDesc_NC \ ((uint32_t)0x00000400) /* No Carrier: no carrier signal from the tranceiver \ */ #define ETH_DMATxDesc_LCO \ ((uint32_t)0x00000200) /* Late Collision: transmission aborted due to \ collision */ #define ETH_DMATxDesc_EC \ ((uint32_t)0x00000100) /* Excessive Collision: transmission aborted after 16 \ collisions */ #define ETH_DMATxDesc_VF ((uint32_t)0x00000080) /* VLAN Frame */ #define ETH_DMATxDesc_CC ((uint32_t)0x00000078) /* Collision Count */ #define ETH_DMATxDesc_ED ((uint32_t)0x00000004) /* Excessive Deferral */ #define ETH_DMATxDesc_UF \ ((uint32_t)0x00000002) /* Underflow Error: late data arrival from the memory \ */ #define ETH_DMATxDesc_DB ((uint32_t)0x00000001) /* Deferred Bit */ /* Field definition of TDES1 register */ #define ETH_DMATxDesc_TBS2 ((uint32_t)0x1FFF0000) /* Transmit Buffer2 Size */ #define ETH_DMATxDesc_TBS1 ((uint32_t)0x00001FFF) /* Transmit Buffer1 Size */ /* Field definition of TDES2 register */ #define ETH_DMATxDesc_B1AP ((uint32_t)0xFFFFFFFF) /* Buffer1 Address Pointer \ */ /* Field definition of TDES3 register */ #define ETH_DMATxDesc_B2AP ((uint32_t)0xFFFFFFFF) /* Buffer2 Address Pointer \ */ /** DMA Rx Desciptor --------------------------------------------------------------------------------------------------------------------- RDES0 | OWN(31) | Status [30:0] | --------------------------------------------------------------------------------------------------------------------- RDES1 | CTRL(31) | Reserved[30:29] | Buffer2 ByteCount[28:16] | CTRL[15:14] | Reserved(13) | Buffer1 ByteCount[12:0] | --------------------------------------------------------------------------------------------------------------------- RDES2 | Buffer1 Address [31:0] | --------------------------------------------------------------------------------------------------------------------- RDES3 | Buffer2 Address [31:0] / Next Desciptor Address [31:0] | ---------------------------------------------------------------------------------------------------------------------- */ /* Bit or field definition of RDES0 register (DMA Rx descriptor status register) */ #define ETH_DMARxDesc_OWN \ ((uint32_t)0x80000000) /* OWN bit: descriptor is owned by DMA engine */ #define ETH_DMARxDesc_AFM \ ((uint32_t)0x40000000) /* DA Filter Fail for the rx frame */ #define ETH_DMARxDesc_FL \ ((uint32_t)0x3FFF0000) /* Receive descriptor frame length */ #define ETH_DMARxDesc_ES \ ((uint32_t)0x00008000) /* Error summary: OR of the following bits: DE || OE \ || IPC || LC || RWT || RE || CE */ #define ETH_DMARxDesc_DE \ ((uint32_t)0x00004000) /* Desciptor error: no more descriptors for receive \ frame */ #define ETH_DMARxDesc_SAF \ ((uint32_t)0x00002000) /* SA Filter Fail for the received frame */ #define ETH_DMARxDesc_LE \ ((uint32_t)0x00001000) /* Frame size not matching with length field */ #define ETH_DMARxDesc_OE \ ((uint32_t)0x00000800) /* Overflow Error: Frame was damaged due to buffer \ overflow */ #define ETH_DMARxDesc_VLAN \ ((uint32_t)0x00000400) /* VLAN Tag: received frame is a VLAN frame */ #define ETH_DMARxDesc_FS \ ((uint32_t)0x00000200) /* First descriptor of the frame */ #define ETH_DMARxDesc_LS \ ((uint32_t)0x00000100) /* Last descriptor of the frame */ #define ETH_DMARxDesc_IPV4HCE \ ((uint32_t)0x00000080) /* IPC Checksum Error: Rx Ipv4 header checksum error \ */ #define ETH_DMARxDesc_LC \ ((uint32_t)0x00000040) /* Late collision occurred during reception */ #define ETH_DMARxDesc_FT \ ((uint32_t)0x00000020) /* Frame type - Ethernet, otherwise 802.3 */ #define ETH_DMARxDesc_RWT \ ((uint32_t)0x00000010) /* Receive Watchdog Timeout: watchdog timer expired \ during reception */ #define ETH_DMARxDesc_RE \ ((uint32_t)0x00000008) /* Receive error: error reported by MII interface */ #define ETH_DMARxDesc_DBE \ ((uint32_t)0x00000004) /* Dribble bit error: frame contains non int multiple \ of 8 bits */ #define ETH_DMARxDesc_CE ((uint32_t)0x00000002) /* CRC error */ #define ETH_DMARxDesc_MAMPCE \ ((uint32_t)0x00000001) /* Rx MAC Address/Payload Checksum Error: Rx MAC \ address matched/ Rx Payload Checksum Error */ /* Bit or field definition of RDES1 register */ #define ETH_DMARxDesc_DIC \ ((uint32_t)0x80000000) /* Disable Interrupt on Completion */ #define ETH_DMARxDesc_RBS2 ((uint32_t)0x1FFF0000) /* Receive Buffer2 Size */ #define ETH_DMARxDesc_RER ((uint32_t)0x00008000) /* Receive End of Ring */ #define ETH_DMARxDesc_RCH ((uint32_t)0x00004000) /* Second Address Chained */ #define ETH_DMARxDesc_RBS1 ((uint32_t)0x00001FFF) /* Receive Buffer1 Size */ /* Field definition of RDES2 register */ #define ETH_DMARxDesc_B1AP ((uint32_t)0xFFFFFFFF) /* Buffer1 Address Pointer \ */ /* Field definition of RDES3 register */ #define ETH_DMARxDesc_B2AP ((uint32_t)0xFFFFFFFF) /* Buffer2 Address Pointer \ */ #define ETH_DMARxDesc_FrameLengthShift 16 typedef struct { uint32_t volatile Status; /* Status */ uint32_t ControlBufferSize; /* Control and Buffer1, Buffer2 lengths */ uint32_t Buffer1Addr; /* Buffer1 address pointer */ uint32_t Buffer2NextDescAddr; /* Buffer2 or next descriptor address pointer */ } ETH_DMADESCTypeDef; /** * @brief Initialize the ethernet interface and lwIP network stack. * This function should be passed as the init function to netif_add(). * * @param netif The lwIP network interface structure to be initialized. * @return ERR_OK if the loopif is initialized, ERR_MEM if private data couldn't * be allocated. */ err_t ethernetif_init(struct netif* netif); /** * @brief This function should be called periodically from your main loop * to check for incoming packets and pass them to lwIP. * * @param netif The lwIP network interface structure. */ void ethernetif_input(struct netif* netif); /** * @brief This function should be called periodically from your main loop * to check the link status and update lwIP accordingly. * * @param netif The lwIP network interface structure.. */ void ethernetif_link_poll(struct netif* netif); #endif /* __ETHERNETIF_H */