256 lines
7.1 KiB
C
256 lines
7.1 KiB
C
#include "ethernetif.h"
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#include <stdbool.h>
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#include <stdio.h>
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#include <string.h>
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#include "ch32fun.h"
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#include "ch32v20xhw.h"
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#include "lwip/etharp.h"
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#include "lwip/snmp.h"
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#include "systick.h"
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#define IFNAME0 'e'
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#define IFNAME1 'n'
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#define ETH_RXBUFNB 4
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#define ETH_TXBUFNB 1
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#define ETH_MAX_PACKET_SIZE 1520
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#define ETH_RX_BUF_SZE ETH_MAX_PACKET_SIZE
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#define ETH_TX_BUF_SZE ETH_MAX_PACKET_SIZE
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struct ethernetif {
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ETH_DMADESCTypeDef* DMARxDescToGet;
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ETH_DMADESCTypeDef* DMATxDescToSet;
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};
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__attribute__((aligned(4))) ETH_DMADESCTypeDef DMARxDscrTab[ETH_RXBUFNB];
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__attribute__((aligned(4))) ETH_DMADESCTypeDef DMATxDscrTab[ETH_TXBUFNB];
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__attribute__((aligned(4))) uint8_t MACRxBuf[ETH_RXBUFNB * ETH_RX_BUF_SZE];
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__attribute__((aligned(4))) uint8_t MACTxBuf[ETH_TXBUFNB * ETH_TX_BUF_SZE];
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static volatile bool g_link_interrupt_flag = false;
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static void low_level_init(struct netif* netif);
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static err_t low_level_output(struct netif* netif, struct pbuf* p);
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static struct pbuf* low_level_input(struct netif* netif);
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void WritePHYReg(uint8_t reg_add, uint16_t reg_val);
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uint16_t ReadPHYReg(uint8_t reg_add);
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static void eth_get_mac_in_uc(uint8_t* mac) {
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// Mac is backwards.
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const uint8_t* macaddr = (const uint8_t*)(ROM_CFG_USERADR_ID + 5);
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for (int i = 0; i < 6; i++) {
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mac[i] = *(macaddr--);
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}
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}
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err_t ethernetif_init(struct netif* netif) {
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struct ethernetif* ethernetif = mem_malloc(sizeof(struct ethernetif));
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if (ethernetif == NULL) {
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LWIP_DEBUGF(NETIF_DEBUG, ("ethernetif_init: out of memory\n"));
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return ERR_MEM;
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}
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#if LWIP_NETIF_HOSTNAME
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netif->hostname = "lwip-ch32";
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#endif
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netif->state = ethernetif;
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netif->name[0] = IFNAME0;
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netif->name[1] = IFNAME1;
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netif->output = etharp_output;
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netif->linkoutput = low_level_output;
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MIB2_INIT_NETIF(netif, snmp_ifType_ethernet_csmacd, 10000000); // 10Mbps
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netif->hwaddr_len = ETH_HWADDR_LEN;
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uint8_t mac_addr[6];
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eth_get_mac_in_uc(mac_addr);
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printf("MAC Address: %02X:%02X:%02X:%02X:%02X:%02X\n", mac_addr[0],
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mac_addr[1], mac_addr[2], mac_addr[3], mac_addr[4], mac_addr[5]);
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/* set MAC hardware address */
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netif->hwaddr[0] = mac_addr[0];
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netif->hwaddr[1] = mac_addr[1];
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netif->hwaddr[2] = mac_addr[2];
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netif->hwaddr[3] = mac_addr[3];
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netif->hwaddr[4] = mac_addr[4];
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netif->hwaddr[5] = mac_addr[5];
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netif->mtu = 1500;
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netif->flags = NETIF_FLAG_BROADCAST | NETIF_FLAG_ETHARP;
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low_level_init(netif);
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return ERR_OK;
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}
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static void low_level_init(struct netif* netif) {
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struct ethernetif* ethernetif = netif->state;
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// clocks
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RCC->APB2PCENR |= RCC_APB2Periph_AFIO;
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RCC->CFGR0 = (RCC->CFGR0 & ~((uint32_t)1 << 28)) | (RCC_ETHCLK_Div2 << 28);
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EXTEN->EXTEN_CTR |= EXTEN_ETH_10M_EN;
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// mac reset
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ETH10M->ECON1 |= (RB_ETH_ECON1_TXRST | RB_ETH_ECON1_RXRST);
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ETH10M->ECON1 &= ~(RB_ETH_ECON1_TXRST | RB_ETH_ECON1_RXRST);
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// mac regs
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ETH10M->ERXFON = RB_ETH_ERXFCON_BCEN | RB_ETH_ERXFCON_MCEN;
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ETH10M->MACON1 = RB_ETH_MACON1_MARXEN;
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ETH10M->MACON2 = PADCFG_AUTO_3 | RB_ETH_MACON2_TXCRCEN;
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ETH10M->MAMXFL = ETH_MAX_PACKET_SIZE;
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R8_ETH_MAADRL1 = netif->hwaddr[5];
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R8_ETH_MAADRL2 = netif->hwaddr[4];
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R8_ETH_MAADRL3 = netif->hwaddr[3];
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R8_ETH_MAADRL4 = netif->hwaddr[2];
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R8_ETH_MAADRL5 = netif->hwaddr[1];
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R8_ETH_MAADRL6 = netif->hwaddr[0];
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// PHY analog block
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ETH10M->ECON2 = (ETH10M->ECON2 & ~(0x07 << 1)) | (5 << 1);
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// DMA descriptors
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ethernetif->DMATxDescToSet = &DMATxDscrTab[0];
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DMATxDscrTab[0].Status = 0;
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DMATxDscrTab[0].Buffer1Addr = (uint32_t)MACTxBuf;
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DMATxDscrTab[0].Buffer2NextDescAddr = (uint32_t)&DMATxDscrTab[0];
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ethernetif->DMARxDescToGet = &DMARxDscrTab[0];
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for (int i = 0; i < ETH_RXBUFNB; i++) {
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DMARxDscrTab[i].Status = 0;
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DMARxDscrTab[i].Buffer1Addr = (uint32_t)(&MACRxBuf[i * ETH_RX_BUF_SZE]);
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DMARxDscrTab[i].Buffer2NextDescAddr =
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(uint32_t)(&DMARxDscrTab[(i + 1) % ETH_RXBUFNB]);
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}
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ETH10M->ERXST = (uint32_t)ethernetif->DMARxDescToGet->Buffer1Addr;
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ETH10M->ECON1 |= RB_ETH_ECON1_RXEN;
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printf("Resetting PHY...\n");
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WritePHYReg(PHY_BMCR, PHY_BMCR_RESET);
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Delay_Ms(200);
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printf("Starting PHY, Mode: 10BASE_T_FD\n");
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WritePHYReg(PHY_BMCR, PHY_BMCR_FORCE_10BASE_T_FD);
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ETH10M->EIE = RB_ETH_EIE_INTIE | RB_ETH_EIE_TXIE | RB_ETH_EIE_LINKIE;
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ETH10M->EIR = 0xFF;
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NVIC_EnableIRQ(ETH_IRQn);
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printf("low_level_init: done\n");
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}
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static err_t low_level_output(struct netif* netif, struct pbuf* p) {
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if (DMATxDscrTab[0].Status & ETH_DMATxDesc_OWN) return ERR_BUF;
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uint32_t len = 0;
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uint8_t* tx_buf_ptr = (uint8_t*)DMATxDscrTab[0].Buffer1Addr;
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for (struct pbuf* q = p; q != NULL; q = q->next) {
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memcpy(&tx_buf_ptr[len], q->payload, q->len);
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len += q->len;
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}
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ETH10M->ETXLN = len;
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ETH10M->ETXST = (uint32_t)tx_buf_ptr;
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DMATxDscrTab[0].Status |= ETH_DMATxDesc_OWN;
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ETH10M->ECON1 |= RB_ETH_ECON1_TXRTS;
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MIB2_STATS_NETIF_ADD(netif, ifoutoctets, len);
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return ERR_OK;
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}
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static struct pbuf* low_level_input(struct netif* netif) {
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struct ethernetif* ethernetif = netif->state;
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uint16_t len;
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uint8_t* current_rx_buffer_ptr;
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if ((ETH10M->EIR & RB_ETH_EIR_RXIF) == 0) return NULL;
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len = ETH10M->ERXLN;
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current_rx_buffer_ptr = (uint8_t*)ethernetif->DMARxDescToGet->Buffer1Addr;
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ethernetif->DMARxDescToGet =
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(ETH_DMADESCTypeDef*)ethernetif->DMARxDescToGet->Buffer2NextDescAddr;
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ETH10M->ERXST = (uint32_t)ethernetif->DMARxDescToGet->Buffer1Addr;
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ETH10M->ECON1 |= RB_ETH_ECON1_RXEN;
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struct pbuf* p = NULL;
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if (len > 0) {
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p = pbuf_alloc(PBUF_RAW, len, PBUF_POOL);
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if (p != NULL) {
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uint32_t bytes_copied = 0;
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for (struct pbuf* q = p; q != NULL; q = q->next) {
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memcpy(q->payload, current_rx_buffer_ptr + bytes_copied, q->len);
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bytes_copied += q->len;
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}
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MIB2_STATS_NETIF_ADD(netif, ifinoctets, len);
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} else {
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MIB2_STATS_NETIF_INC(netif, ifindiscards);
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}
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}
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ETH10M->EIR = RB_ETH_EIR_RXIF;
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return p;
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}
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void ethernetif_input(struct netif* netif) {
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struct pbuf* p;
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while ((p = low_level_input(netif)) != NULL) {
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if (netif->input(p, netif) != ERR_OK) {
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pbuf_free(p);
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}
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}
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}
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void ethernetif_link_poll(struct netif* netif) {
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if (!g_link_interrupt_flag) {
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return;
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}
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g_link_interrupt_flag = false;
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uint16_t bmsr = ReadPHYReg(PHY_BMSR);
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if (bmsr & PHY_BMSR_LINK_STATUS) {
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if (!netif_is_link_up(netif)) {
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printf("Link is UP\n");
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ETH10M->MACON2 |= RB_ETH_MACON2_FULDPX;
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netif_set_link_up(netif);
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}
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} else {
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if (netif_is_link_up(netif)) {
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printf("Link is DOWN\n");
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netif_set_link_down(netif);
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}
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}
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}
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void ETH_IRQHandler(void) __attribute__((interrupt));
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void ETH_IRQHandler(void) {
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uint32_t flags = ETH10M->EIR;
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if (flags & RB_ETH_EIR_TXIF) {
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DMATxDscrTab[0].Status &= ~ETH_DMATxDesc_OWN;
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ETH10M->EIR = RB_ETH_EIR_TXIF;
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}
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if (flags & RB_ETH_EIR_LINKIF) {
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g_link_interrupt_flag = true;
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ETH10M->EIR = RB_ETH_EIR_LINKIF;
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}
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}
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void WritePHYReg(uint8_t reg_add, uint16_t reg_val) {
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R32_ETH_MIWR = (reg_add & RB_ETH_MIREGADR_MIRDL) | (1 << 8) | (reg_val << 16);
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}
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uint16_t ReadPHYReg(uint8_t reg_add) {
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ETH10M->MIERGADR = reg_add;
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return ETH10M->MIRD;
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}
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