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19
rtl8710.ld
Normal file
19
rtl8710.ld
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MEMORY{
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tcm (rwx) : ORIGIN = 0x1FFF0000, LENGTH = 64k
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ram (rwx) : ORIGIN = 0x10000000, LENGTH = 448k
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}
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PROVIDE(STACK_TOP = 0x1FFF0000 + 64k);
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SECTIONS{
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.text : { __text_beg__ = . ; *(.vectors*) *(.header) *(.text) *(.text*) *(.rodata) *(.rodata*) *(.glue_7) *(.glue_7t) *(.eh_frame) *(.ARM.extab*) . = ALIGN(4); __text_end__ = . ; } >ram
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.data : { . = ALIGN(4); __data_beg__ = . ; *(.ram_vectors) *(.data) *(.data*) *(.ram_func) . = ALIGN(4); __data_end__ = . ; } >ram
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.bss : { . = ALIGN(4); __bss_beg__ = . ; *(.bss) *(COMMON) . = ALIGN(4); __bss_end__ = . ; } >ram
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__exidx_start = .;
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.ARM.exidx : { ___exidx_start = . ; *(.ARM.exidx*) ; ___exidx_end = . ; } >ram
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__exidx_end = .;
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.ARM.extab : { *(.ARM.extab*) } >ram
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. = ALIGN(4);
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end = .; PROVIDE (end = .);
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}
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