mira/rtl8710bx-re
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fix: lxbus

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Mira
2024-12-07 17:19:29 +06:00
parent 535abe4b13
commit 2f5f9dfe40
1 changed files with 54 additions and 25 deletions
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79
include/rtl8710bx.h
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@@ -823,39 +823,68 @@ typedef struct {
* spacing between TX descriptors is unusual * spacing between TX descriptors is unusual
* 32K control register (at 0x3D9)??? * 32K control register (at 0x3D9)???
*/ */
// void __fastcall ROM_WIFI_InitLxDma_patch(rtw_tx_ring *tx_ring, rtw_rx_ring
// *rx_ring, uint32_t test_mode)
// {
// dword_40080300 &= ~0x100u;
// dword_400803E8 = 0xFFFFFF;
// word_40080380 = 0x1004;
// word_40080382 = 0x2004;
// word_40080384 = 0x1004;
// word_40080386 = 0x1004;
// word_40080388 = 0x1004;
// word_4008038A = 0x1004;
// word_4008038C = 0x1002;
// word_4008038E = 0x1002;
// word_40080390 = 0x1002;
// word_40080392 = 0x1002;
// word_40080394 = 0x1002;
// word_40080396 = 0x1002;
// word_40080398 = 0x1002;
// word_4008039A = 0x1002;
// dword_40080318 = (int)tx_ring->desc;
// dword_40080320 = (int)tx_ring[1].desc;
// dword_40080328 = (int)tx_ring[2].desc;
// dword_40080330 = (int)tx_ring[3].desc;
// dword_40080308 = (int)tx_ring[4].desc;
// dword_40080310 = (int)tx_ring[5].desc;
// dword_40080340 = (int)tx_ring[6].desc;
// dword_40080338 = (int)rx_ring->desc;
// dword_4008020C |= 0x10000000u;
// }
/* 0x0300h ~ 0x03FFh LxBUS Registers */
typedef struct { typedef struct {
/* 0x0300 - Control Register */ /* 0x0300 - Control Register */
volatile uint32_t CTRL; /* 0x0300 - Control register */ __IO uint32_t CTRL; /* 0x0300 - Control register */
volatile uint32_t RESERVED1[1]; /* 0x0304 */ __IO uint32_t RESERVED1[1]; /* 0x0304 */
volatile uint32_t TX4_DESC; /* 0x0308 - TX Ring 4 Descriptor */ __IO uint32_t TX4_DESC; /* 0x0308 - TX Ring 4 Descriptor */
volatile uint32_t RESERVED2[1]; /* 0x030C */ __IO uint32_t RESERVED2[1]; /* 0x030C */
volatile uint32_t TX5_DESC; /* 0x0310 - TX Ring 5 Descriptor */ __IO uint32_t TX5_DESC; /* 0x0310 - TX Ring 5 Descriptor */
volatile uint32_t RESERVED3[1]; /* 0x0314 */ __IO uint32_t RESERVED3[1]; /* 0x0314 */
volatile uint32_t TX0_DESC; /* 0x0318 - TX Ring 0 Descriptor */ __IO uint32_t TX0_DESC; /* 0x0318 - TX Ring 0 Descriptor */
volatile uint32_t RESERVED4[1]; /* 0x031C */ __IO uint32_t RESERVED4[1]; /* 0x031C */
volatile uint32_t TX1_DESC; /* 0x0320 - TX Ring 1 Descriptor */ __IO uint32_t TX1_DESC; /* 0x0320 - TX Ring 1 Descriptor */
volatile uint32_t RESERVED5[1]; /* 0x0324 */ __IO uint32_t RESERVED5[1]; /* 0x0324 */
volatile uint32_t TX2_DESC; /* 0x0328 - TX Ring 2 Descriptor */ __IO uint32_t TX2_DESC; /* 0x0328 - TX Ring 2 Descriptor */
volatile uint32_t RESERVED6[1]; /* 0x032C */ __IO uint32_t RESERVED6[1]; /* 0x032C */
volatile uint32_t TX3_DESC; /* 0x0330 - TX Ring 3 Descriptor */ __IO uint32_t TX3_DESC; /* 0x0330 - TX Ring 3 Descriptor */
volatile uint32_t RESERVED7[1]; /* 0x0334 */ __IO uint32_t RESERVED7[1]; /* 0x0334 */
volatile uint32_t RX_DESC; /* 0x0338 - RX Ring Descriptor */ __IO uint32_t RX_DESC; /* 0x0338 - RX Ring Descriptor */
volatile uint32_t RESERVED8[1]; /* 0x033C */ __IO uint32_t RESERVED8[1]; /* 0x033C */
volatile uint32_t TX6_DESC; /* 0x0340 - TX Ring 6 Descriptor */ __IO uint32_t TX6_DESC; /* 0x0340 - TX Ring 6 Descriptor */
volatile uint32_t RESERVED9[15]; /* 0x0344-0x037F */ __IO uint32_t RESERVED9[15]; /* 0x0344-0x037F */
/* DMA Configuration Registers */ /* DMA Configuration Registers */
volatile uint16_t __IO uint16_t DMA_CFG[14]; /* 0x0380-0x039B - DMA Configuration registers */
DMA_CFG[14]; /* 0x0380-0x039B - DMA Configuration registers */ __IO uint8_t RESERVED10[61]; /* 0x039C-0x03D8 */
volatile uint8_t RESERVED10[61]; /* 0x039C-0x03D8 */
/* 32K Control Register */ /* 32K Control Register */
volatile uint8_t K32_CTRL; /* 0x03D9 - 32K Control register */ __IO uint8_t K32_CTRL; /* 0x03D9 - 32K Control register */
volatile uint8_t RESERVED11[14]; /* 0x03DA-0x03E7 */ __IO uint8_t RESERVED11[14]; /* 0x03DA-0x03E7 */
/* Additional Control Registers */ /* Additional Control Registers */
volatile uint32_t INT_MASK; /* 0x03E8 - Interrupt Mask */ __IO uint32_t INT_MASK; /* 0x03E8 - Interrupt Mask */
volatile uint32_t INT_STATUS; /* 0x03EC - Interrupt Status */ __I uint32_t INT_STATUS; /* 0x03EC - Interrupt Status */
} WiFi_LXBUS_TypeDef; } WiFi_LXBUS_TypeDef;
/* bits */ /* bits */
#define LXBUS_CTRL_BIT8 (1 << 8) /* Control register bit 8 */ #define LXBUS_CTRL_BIT8 (1 << 8) /* Control register bit 8 */