chore: clock stuff, wlan
This commit is contained in:
261
src/main.c
261
src/main.c
@@ -1,39 +1,258 @@
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#include <stdint.h>
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#include <strings.h>
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#include "rtl8710bx.h"
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extern uint32_t DiagPrintf(const char *fmt, ...)
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__attribute__((format(printf, 1, 2)));
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extern void DelayMs(uint32_t ms);
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#define printf DiagPrintf
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static inline void delay_cycles(unsigned int count) {
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__asm volatile(
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"1: \n"
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" subs %[count], %[count], #1 \n"
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" bne 1b \n"
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: [count] "+r"(count)
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:
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: "cc");
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typedef struct {
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char ssid[33];
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uint8_t bssid[6];
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uint8_t channel;
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int8_t rssi;
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} Network_Info_t;
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static void wifi_init(void) {
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PERI_ON->PESOC_CLK_CTRL |=
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BIT_SOC_ACTCK_BTCMD_EN | BIT_SOC_ACTCK_VENDOR_REG_EN;
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PERI_ON->SOC_HCI_COM_FUNC_EN |= BIT_SOC_HCI_WL_MACON_EN;
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WIFI->SYS.FUNC_EN |= FEN_MREGEN;
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WIFI->SYS.APS_FSMCO |= APFM_ONMAC;
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WIFI->SYS.APS_FSMCO &= ~SUS_HOST;
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WIFI->SYS.ISO_CTRL &= ~PWC_EV12V;
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// printf("waiting for APS_FSMCO\n");
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// while (!(wifi->SYS.APS_FSMCO & RDY_MACON));
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// printf("RDY_MACON\n");
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WIFI->WMAC.RCR |= (BM_DATA_EN | UC_DATA_EN); // broadcast, unicast
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WIFI->MAC.CR |= MACRXEN; // en RX
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}
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static inline void delay_ms(unsigned int ms) {
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for (unsigned int i = 0; i < ms; i++) {
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delay_cycles(15625); // 62500/4 cycles
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void print_wifi_version(void) {
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printf("SYSTEM_CFG0 address: 0x%08X\n", (uint32_t)&SYSTEM_CTRL->SYSTEM_CFG0);
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printf("SYSTEM_CFG0: 0x%08X\n", SYSTEM_CTRL->SYSTEM_CFG0);
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// printf("SYSTEM_CFG1 address: 0x%08X\n",
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// (uint32_t)&SYSTEM_CTRL->SYSTEM_CFG1); printf("SYSTEM_CFG1: 0x%08X\n",
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// SYSTEM_CTRL->SYSTEM_CFG1); printf("SYSTEM_CFG2 address: 0x%08X\n",
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// (uint32_t)&SYSTEM_CTRL->SYSTEM_CFG2); printf("SYSTEM_CFG2: 0x%08X\n",
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// SYSTEM_CTRL->SYSTEM_CFG2);
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// uint32_t xtal_type = ((cfg ^ 0x10000) >> 16) & 1;
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// uint32_t cut_id = (cfg >> 8) & 3;
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// uint32_t chip_id = (cfg >> 4) & 0xF;
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// uint32_t revision;
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// if (cut_id == 1)
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// revision = 2;
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// else if (cut_id == 2)
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// revision = 1;
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// else
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// revision = 0;
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// printf("SYSCFG0: 0x%08X\n", cfg);
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// printf("Version: 11\n");
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// printf("XTAL Type: 0x%x\n", xtal_type);
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// printf("Chip ID: 0x%x\n", chip_id);
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// printf("Revision: 0x%x\n", revision);
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}
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#define CLK_TABLE_ROM 0x00046E68
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#define XTAL_TABLE_ROM 0x000046E10
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/* REG_SYS_CLK_CTRL1 */
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#define BIT_PESOC_EXT32K_CK_SEL (0x00000001 << 8)
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#define BIT_PESOC_OCP_CPU_CK_SEL (0x00000007 << 4)
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#define BIT_PESOC_EELDR_CK_SEL (0x00000001 << 0)
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/* REG_SYS_SYSPLL_CTRL1 */
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/* 1:200MHz, 0:166.666MHz */
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#define BIT_SYS_SYSPLL_CL200M_SEL (0x00000001 << 17)
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/* 1:external source 0:PLL */
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#define BIT_SYS_SYSPLL_CK500K_SEL (0x00000001 << 15)
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/* enable CK200M */
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#define BIT_SYS_SYSPLL_CK200M_EN (0x00000001 << 14)
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/* 1: enable CK_SDRAM */
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#define BIT_SYS_SYSPLL_CKSDR_EN (0x00000001 << 13)
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/* SDR PLL select: 00/01/10/11 no clock/25M/50M/100M */
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#define BIT_SYS_SYSPLL_CKSDR_DIV (0x00000003 << 11)
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/* 1:enable CK24.576M PLL */
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#define BIT_SYS_SYSPLL_CK24P576_EN (0x00000001 << 10)
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/* 1: enable CK22.5792M PLL */
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#define BIT_SYS_SYSPLL_CK22P5792_EN (0x00000001 << 9)
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/* 1: enable CK83.33M PLL */
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#define BIT_SYS_SYSPLL_CK83P33M_EN (0x00000001 << 8)
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/* reg_ps_en Enable phase shift */
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#define BIT_SYS_SYSPLL_CK_PS_EN (0x00000001 << 7)
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/* "decide clock phase when reg_ps_enb = 1000/001<30><31>/111: phase 0, 45<34><35>315 */
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#define BIT_SYS_SYSPLL_CK_PS_SEL (0x00000007 << 4)
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/* REG_SYS_EFUSE_SYSCFG2 */
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#define BIT_MASK_SYS_EERROM_ANAPAR_SPLL_24_15 (0x000003ff << 21)
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#define BIT_MASK_SYS_EEROM_ANAPAR_SPLL_05_02 (0x0000000f << 16)
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#define BIT_MASK_SYS_EEROM_XTAL_STEL_SEL (0x00000003 << 12)
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#define BIT_MASK_SYS_EEROM_XTAL_FREQ_SEL (0x0000000f << 8)
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void dump_hex(const void *data, size_t size, const char *prefix) {
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const uint8_t *bytes = (const uint8_t *)data;
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for (size_t i = 0; i < size; i++) {
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if (i % 16 == 0) printf("\n%s%04zX: ", prefix, i);
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printf("%02X ", bytes[i]);
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}
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printf("\n");
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}
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void analyze_clock_config(void) {
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printf("\n=== CLOCK CONFIGURATION ===\n");
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// all releveant regs
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printf("\nRegister Values (Raw):\n");
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printf("CLK_CTRL1: 0x%08X\n", SYSTEM_CTRL->CLK_CTRL1);
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printf("SYSPLL_CTRL1: 0x%08X\n", SYSTEM_CTRL->SYSPLL_CTRL1);
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printf("EFUSE_SYSCFG2: 0x%08X\n", SYSTEM_CTRL->EFUSE_SYSCFG[2]);
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// CLK_CTRL1
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uint32_t clk_ctrl1 = SYSTEM_CTRL->CLK_CTRL1;
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printf("\nCLK_CTRL1:\n");
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printf(" EXT32K_CK_SEL: %d\n",
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(clk_ctrl1 & BIT_PESOC_EXT32K_CK_SEL) ? 1 : 0);
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printf(" OCP_CPU_CK_SEL: %d\n",
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(clk_ctrl1 & BIT_PESOC_OCP_CPU_CK_SEL) >> 4);
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printf(" EELDR_CK_SEL: %d\n",
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(clk_ctrl1 & BIT_PESOC_EELDR_CK_SEL) ? 1 : 0);
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// SYSPLL_CTRL1
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uint32_t syspll_ctrl1 = SYSTEM_CTRL->SYSPLL_CTRL1;
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printf("\nSYSPLL_CTRL1:\n");
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printf(" CL200M_SEL: %d\n",
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(syspll_ctrl1 & BIT_SYS_SYSPLL_CL200M_SEL) ? 1 : 0);
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printf(" CK500K_SEL: %d\n",
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(syspll_ctrl1 & BIT_SYS_SYSPLL_CK500K_SEL) ? 1 : 0);
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printf(" CK200M_EN: %d\n",
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(syspll_ctrl1 & BIT_SYS_SYSPLL_CK200M_EN) ? 1 : 0);
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printf(" CKSDR_EN: %d\n",
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(syspll_ctrl1 & BIT_SYS_SYSPLL_CKSDR_EN) ? 1 : 0);
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printf(" CKSDR_DIV: %d\n",
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(syspll_ctrl1 & BIT_SYS_SYSPLL_CKSDR_DIV) >> 11);
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printf(" CK24P576_EN: %d\n",
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(syspll_ctrl1 & BIT_SYS_SYSPLL_CK24P576_EN) ? 1 : 0);
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printf(" CK22P5792_EN: %d\n",
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(syspll_ctrl1 & BIT_SYS_SYSPLL_CK22P5792_EN) ? 1 : 0);
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printf(" CK83P33M_EN: %d\n",
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(syspll_ctrl1 & BIT_SYS_SYSPLL_CK83P33M_EN) ? 1 : 0);
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printf(" CK_PS_EN: %d\n",
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(syspll_ctrl1 & BIT_SYS_SYSPLL_CK_PS_EN) ? 1 : 0);
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printf(" CK_PS_SEL: %d\n",
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(syspll_ctrl1 & BIT_SYS_SYSPLL_CK_PS_SEL) >> 4);
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// EFUSE_SYSCFG2
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uint32_t efuse_syscfg2 = SYSTEM_CTRL->EFUSE_SYSCFG[2];
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uint32_t spll_24_15 =
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(efuse_syscfg2 & BIT_MASK_SYS_EERROM_ANAPAR_SPLL_24_15) >> 21;
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uint32_t spll_05_02 =
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(efuse_syscfg2 & BIT_MASK_SYS_EEROM_ANAPAR_SPLL_05_02) >> 16;
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uint32_t xtal_stel_sel =
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(efuse_syscfg2 & BIT_MASK_SYS_EEROM_XTAL_STEL_SEL) >> 12;
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uint32_t xtal_freq_sel =
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(efuse_syscfg2 & BIT_MASK_SYS_EEROM_XTAL_FREQ_SEL) >> 8;
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printf("\nEFUSE_SYSCFG2:\n");
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printf(" SPLL 24:15 Config: 0x%03X\n", spll_24_15);
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printf(" SPLL 05:02 Config: 0x%X\n", spll_05_02);
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printf(" XTAL_STEL_SEL: 0x%X\n", xtal_stel_sel);
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printf(" XTAL_FREQ_SEL: 0x%X\n", xtal_freq_sel);
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// rom XTAL table
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printf("\nXTAL Table Contents (first 16 entries):\n");
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const uint32_t *xtal_table = (const uint32_t *)XTAL_TABLE_ROM;
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for (int i = 0; i < 16; i++) {
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printf(" [%d]: %d (0x%x Hz)\n", i, xtal_table[i], xtal_table[i]);
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}
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// xtal freq
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uint32_t xtal_freq = xtal_table[xtal_freq_sel];
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printf("\nSelected Crystal:\n");
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printf(" Index: %d\n", xtal_freq_sel);
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printf(" Frequency: %d Hz (0x%08X)\n", xtal_freq, xtal_freq);
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// dump clock table
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printf("\nClock Table Contents (first 16 entries):\n");
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const uint8_t *clk_table = (uint8_t *)CLK_TABLE_ROM;
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for (int i = 0; i < 16; i++) {
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printf(" [%2d]: %d MHz (0x%x)\n", i, clk_table[i], clk_table[i]);
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}
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// PLL freq
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uint32_t pll_base_freq =
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(syspll_ctrl1 & BIT_SYS_SYSPLL_CL200M_SEL) ? 200000000 : 166666666;
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printf("\nPLL Frequencies:\n");
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printf(" Base: %d Hz (0x%x)\n", pll_base_freq, pll_base_freq);
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printf(
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" SDR Clock: %d Hz (if enabled)\n",
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pll_base_freq >> (2 - ((syspll_ctrl1 & BIT_SYS_SYSPLL_CKSDR_DIV) >> 11)));
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printf(" 83.33M: %d Hz (if enabled)\n", 83330000);
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printf(" 24.576M: %d Hz (if enabled)\n", 24576000);
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printf(" 22.5792M: %d Hz (if enabled)\n", 22579200);
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// some rom table
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uint32_t cpu_clock_sel = (clk_ctrl1 & BIT_PESOC_OCP_CPU_CK_SEL) >> 4;
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uint32_t cpu_freq = clk_table[cpu_clock_sel];
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printf("\nCPU Configuration:\n");
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printf(" Clock Selection Index: %d\n", cpu_clock_sel);
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printf(" Frequency: %d MHz (0x%x)\n", cpu_freq, cpu_freq);
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uint32_t xtal_to_pll = (pll_base_freq / (xtal_freq / 1000));
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uint32_t pll_to_cpu =
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((uint32_t)(cpu_freq * 1000000UL) / (pll_base_freq / 1000));
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uint32_t xtal_to_cpu =
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((uint32_t)(cpu_freq * 1000000UL) / (xtal_freq / 1000));
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printf("\nFrequency Relationships (x1000):\n");
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printf(" XTAL to PLL Base: %x.%03x\n", xtal_to_pll / 1000,
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xtal_to_pll % 1000);
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printf(" PLL Base to CPU: %x.%03x\n", pll_to_cpu / 1000, pll_to_cpu % 1000);
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printf(" XTAL to CPU: %x.%03x\n", xtal_to_cpu / 1000,
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xtal_to_cpu % 1000);
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}
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int main(void) {
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printf("hello from main\n");
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printf("[main]\n");
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PERI_ON->SOC_PERI_FUNC1_EN |= BIT_PERI_GPIO_EN;
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PERI_ON->PESOC_CLK_CTRL |= APBPeriph_GPIO_CLOCK;
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PINMUX_Config(_PA_0, PINMUX_FN_GPIO);
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PINMUX_ConfigPadPull(_PA_0, GPIO_PuPd_DOWN);
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GPIOA->DDR |= (1 << 0);
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uint32_t primask = __get_PRIMASK();
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__disable_irq();
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SYSTEM_CTRL->CLK_CTRL1 = (SYSTEM_CTRL->CLK_CTRL1 & ~0x70) | (2 << 4);
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if (!primask) {
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__enable_irq();
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}
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analyze_clock_config();
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// __asm volatile("udf #0");
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// DelayMs(5000);
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// NVIC_SystemReset();
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// print_wifi_version();
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// wifi_init();
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// delay_ms(3000);
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// PERI_ON->SOC_PERI_FUNC1_EN |= BIT_PERI_GPIO_EN;
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// PERI_ON->PESOC_CLK_CTRL |= APBPeriph_GPIO_CLOCK;
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// PINMUX_Config(_PA_0, PINMUX_FN_GPIO);
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// PINMUX_ConfigPadPull(_PA_0, GPIO_PuPd_DOWN);
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// GPIOA->DDR |= (1 << 0);
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// uint32_t c = 0;
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while (1) {
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GPIOA->DR |= (1 << 0);
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delay_ms(2000);
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GPIOA->DR &= ~(1 << 0);
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delay_ms(2000);
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// GPIOA->DR |= (1 << 0);
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// delay_ms(1000);
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// GPIOA->DR &= ~(1 << 0);
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// delay_ms(1000);
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}
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}
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