chore: clock stuff, wlan
This commit is contained in:
2
Makefile
2
Makefile
@@ -13,7 +13,7 @@ LD_FILE=linker.ld
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RAM_START := 0x10002000
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CFLAGS = -mcpu=$(MCU) -mthumb \
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CFLAGS = -mcpu=$(MCU) -mthumb -mfloat-abi=hard -lm \
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-Wall -Wextra -g3 \
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-Os -ffunction-sections -fdata-sections \
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-nostartfiles -Wl,-T,$(LD_FILE) -u main -Wl,--gc-sections \
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189
include/odm_stuff.h
Normal file
189
include/odm_stuff.h
Normal file
@@ -0,0 +1,189 @@
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/* @2 RF REG LIST */
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#define ODM_REG_RF_MODE_11N 0x00
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#define ODM_REG_RF_0B_11N 0x0B
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#define ODM_REG_CHNBW_11N 0x18
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#define ODM_REG_RF_1D_11N 0x1D
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#define ODM_REG_T_METER_11N 0x24
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#define ODM_REG_RF_25_11N 0x25
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#define ODM_REG_RF_26_11N 0x26
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#define ODM_REG_RF_27_11N 0x27
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#define ODM_REG_RF_2B_11N 0x2B
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#define ODM_REG_RF_2C_11N 0x2C
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#define ODM_REG_RXRF_A3_11N 0x3C
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#define ODM_REG_T_METER_92D_11N 0x42
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#define ODM_REG_T_METER_88E_11N 0x42
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#define ODM_REF_RF_DF_11N 0xDF
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/* @2 BB REG LIST
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* PAGE 8
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*/
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#define ODM_REG_BB_CTRL_11N 0x800
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#define ODM_REG_RF_PIN_11N 0x804
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#define ODM_REG_PSD_CTRL_11N 0x808
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#define ODM_REG_TX_ANT_CTRL_11N 0x80C
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#define ODM_REG_BB_PWR_SAV5_11N 0x818
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#define ODM_REG_CCK_RPT_FORMAT_11N 0x824
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#define ODM_REG_CCK_RPT_FORMAT_11N_B 0x82C
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#define ODM_REG_RX_DEFAULT_A_11N 0x858
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#define ODM_REG_RX_DEFAULT_B_11N 0x85A
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#define ODM_REG_BB_PWR_SAV3_11N 0x85C
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#define ODM_REG_ANTSEL_CTRL_11N 0x860
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#define ODM_REG_RX_ANT_CTRL_11N 0x864
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#define ODM_REG_PIN_CTRL_11N 0x870
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#define ODM_REG_BB_PWR_SAV1_11N 0x874
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#define ODM_REG_ANTSEL_PATH_11N 0x878
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#define ODM_REG_BB_3WIRE_11N 0x88C
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#define ODM_REG_SC_CNT_11N 0x8C4
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#define ODM_REG_PSD_DATA_11N 0x8B4
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#define ODM_REG_CCX_PERIOD_11N 0x894
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#define ODM_REG_NHM_TH9_TH10_11N 0x890
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#define ODM_REG_CLM_11N 0x890
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#define ODM_REG_NHM_TH3_TO_TH0_11N 0x898
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#define ODM_REG_NHM_TH7_TO_TH4_11N 0x89c
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#define ODM_REG_NHM_TH8_11N 0xe28
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#define ODM_REG_CLM_READY_11N 0x8b4
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#define ODM_REG_CLM_RESULT_11N 0x8d0
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#define ODM_REG_NHM_CNT_11N 0x8d8
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/* @For struct acs_info, Jeffery, 2014-12-26 */
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#define ODM_REG_NHM_CNT7_TO_CNT4_11N 0x8dc
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#define ODM_REG_NHM_CNT9_TO_CNT8_11N 0x8d0
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#define ODM_REG_NHM_CNT10_TO_CNT11_11N 0x8d4
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/* PAGE 9 */
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#define ODM_REG_BB_CTRL_PAGE9_11N 0x900
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#define ODM_REG_DBG_RPT_11N 0x908
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#define ODM_REG_BB_TX_PATH_11N 0x90c
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#define ODM_REG_ANT_MAPPING1_11N 0x914
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#define ODM_REG_ANT_MAPPING2_11N 0x918
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#define ODM_REG_EDCCA_DOWN_OPT_11N 0x948
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#define ODM_REG_RX_DFIR_MOD_97F 0x948
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#define ODM_REG_SOML_97F 0x998
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/* PAGE A */
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#define ODM_REG_CCK_ANTDIV_PARA1_11N 0xA00
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#define ODM_REG_CCK_ANT_SEL_11N 0xA04
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#define ODM_REG_CCK_CCA_11N 0xA0A
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#define ODM_REG_CCK_ANTDIV_PARA2_11N 0xA0C
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#define ODM_REG_CCK_ANTDIV_PARA3_11N 0xA10
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#define ODM_REG_CCK_ANTDIV_PARA4_11N 0xA14
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#define ODM_REG_CCK_FILTER_PARA1_11N 0xA22
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#define ODM_REG_CCK_FILTER_PARA2_11N 0xA23
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#define ODM_REG_CCK_FILTER_PARA3_11N 0xA24
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#define ODM_REG_CCK_FILTER_PARA4_11N 0xA25
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#define ODM_REG_CCK_FILTER_PARA5_11N 0xA26
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#define ODM_REG_CCK_FILTER_PARA6_11N 0xA27
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#define ODM_REG_CCK_FILTER_PARA7_11N 0xA28
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#define ODM_REG_CCK_FILTER_PARA8_11N 0xA29
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#define ODM_REG_CCK_FA_RST_11N 0xA2C
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#define ODM_REG_CCK_FA_MSB_11N 0xA58
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#define ODM_REG_CCK_FA_LSB_11N 0xA5C
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#define ODM_REG_CCK_CCA_CNT_11N 0xA60
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#define ODM_REG_BB_PWR_SAV4_11N 0xA74
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/* PAGE B */
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#define ODM_REG_LNA_SWITCH_11N 0xB2C
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#define ODM_REG_PATH_SWITCH_11N 0xB30
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#define ODM_REG_RSSI_CTRL_11N 0xB38
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#define ODM_REG_CONFIG_ANTA_11N 0xB68
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#define ODM_REG_RSSI_BT_11N 0xB9C
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#define ODM_REG_RXCK_RFMOD 0xBB0
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#define ODM_REG_EDCCA_DCNF_97F 0xBC0
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/* PAGE C */
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#define ODM_REG_OFDM_FA_HOLDC_11N 0xC00
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#define ODM_REG_BB_RX_PATH_11N 0xC04
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#define ODM_REG_TRMUX_11N 0xC08
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#define ODM_REG_OFDM_FA_RSTC_11N 0xC0C
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#define ODM_REG_DOWNSAM_FACTOR_11N 0xC10
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#define ODM_REG_RXIQI_MATRIX_11N 0xC14
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#define ODM_REG_TXIQK_MATRIX_LSB1_11N 0xC4C
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#define ODM_REG_IGI_A_11N 0xC50
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#define ODM_REG_ANTDIV_PARA2_11N 0xC54
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#define ODM_REG_IGI_B_11N 0xC58
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#define ODM_REG_ANTDIV_PARA3_11N 0xC5C
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#define ODM_REG_L1SBD_PD_CH_11N 0XC6C
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#define ODM_REG_BB_PWR_SAV2_11N 0xC70
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#define ODM_REG_BB_AGC_SET_2_11N 0xc74
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#define ODM_REG_RX_OFF_11N 0xC7C
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#define ODM_REG_TXIQK_MATRIXA_11N 0xC80
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#define ODM_REG_TXIQK_MATRIXB_11N 0xC88
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#define ODM_REG_TXIQK_MATRIXA_LSB2_11N 0xC94
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#define ODM_REG_TXIQK_MATRIXB_LSB2_11N 0xC9C
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#define ODM_REG_RXIQK_MATRIX_LSB_11N 0xCA0
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#define ODM_REG_ANTDIV_PARA1_11N 0xCA4
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#define ODM_REG_SMALL_BANDWIDTH_11N 0xCE4
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#define ODM_REG_OFDM_FA_TYPE1_11N 0xCF0
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/* PAGE D */
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#define ODM_REG_OFDM_FA_RSTD_11N 0xD00
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#define ODM_REG_BB_RX_ANT_11N 0xD04
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#define ODM_REG_BB_ATC_11N 0xD2C
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#define ODM_REG_OFDM_FA_TYPE2_11N 0xDA0
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#define ODM_REG_OFDM_FA_TYPE3_11N 0xDA4
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#define ODM_REG_OFDM_FA_TYPE4_11N 0xDA8
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#define ODM_REG_RPT_11N 0xDF4
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/* PAGE E */
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#define ODM_REG_TXAGC_A_6_18_11N 0xE00
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#define ODM_REG_TXAGC_A_24_54_11N 0xE04
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#define ODM_REG_TXAGC_A_1_MCS32_11N 0xE08
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#define ODM_REG_TXAGC_A_MCS0_3_11N 0xE10
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#define ODM_REG_TXAGC_A_MCS4_7_11N 0xE14
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#define ODM_REG_TXAGC_A_MCS8_11_11N 0xE18
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#define ODM_REG_TXAGC_A_MCS12_15_11N 0xE1C
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#define ODM_REG_EDCCA_DCNF_11N 0xE24
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#define ODM_REG_TAP_UPD_97F 0xE24
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#define ODM_REG_FPGA0_IQK_11N 0xE28
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#define ODM_REG_PAGE_B1_97F 0xE28
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#define ODM_REG_TXIQK_TONE_A_11N 0xE30
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#define ODM_REG_RXIQK_TONE_A_11N 0xE34
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#define ODM_REG_TXIQK_PI_A_11N 0xE38
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#define ODM_REG_RXIQK_PI_A_11N 0xE3C
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#define ODM_REG_TXIQK_11N 0xE40
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#define ODM_REG_RXIQK_11N 0xE44
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#define ODM_REG_IQK_AGC_PTS_11N 0xE48
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#define ODM_REG_IQK_AGC_RSP_11N 0xE4C
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#define ODM_REG_BLUETOOTH_11N 0xE6C
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#define ODM_REG_RX_WAIT_CCA_11N 0xE70
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#define ODM_REG_TX_CCK_RFON_11N 0xE74
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#define ODM_REG_TX_CCK_BBON_11N 0xE78
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#define ODM_REG_OFDM_RFON_11N 0xE7C
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#define ODM_REG_OFDM_BBON_11N 0xE80
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#define ODM_REG_TX2RX_11N 0xE84
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#define ODM_REG_TX2TX_11N 0xE88
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#define ODM_REG_RX_CCK_11N 0xE8C
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#define ODM_REG_RX_OFDM_11N 0xED0
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#define ODM_REG_RX_WAIT_RIFS_11N 0xED4
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#define ODM_REG_RX2RX_11N 0xED8
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#define ODM_REG_STANDBY_11N 0xEDC
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#define ODM_REG_SLEEP_11N 0xEE0
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#define ODM_REG_PMPD_ANAEN_11N 0xEEC
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/* PAGE F */
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#define ODM_REG_PAGE_F_RST_11N 0xF14
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#define ODM_REG_IGI_C_11N 0xF84
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#define ODM_REG_IGI_D_11N 0xF88
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#define ODM_REG_CCK_CRC32_ERROR_CNT_11N 0xF84
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#define ODM_REG_CCK_CRC32_OK_CNT_11N 0xF88
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#define ODM_REG_HT_CRC32_CNT_11N 0xF90
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#define ODM_REG_OFDM_CRC32_CNT_11N 0xF94
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#define ODM_REG_HT_CRC32_CNT_11N_AGG 0xFB8
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/* @2 MAC REG LIST */
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#define ODM_REG_BB_RST_11N 0x02
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#define ODM_REG_ANTSEL_PIN_11N 0x4C
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#define ODM_REG_EARLY_MODE_11N 0x4D0
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#define ODM_REG_RSSI_MONITOR_11N 0x4FE
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#define ODM_REG_EDCA_VO_11N 0x500
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#define ODM_REG_EDCA_VI_11N 0x504
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#define ODM_REG_EDCA_BE_11N 0x508
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#define ODM_REG_EDCA_BK_11N 0x50C
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#define ODM_REG_TXPAUSE_11N 0x522
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#define ODM_REG_RESP_TX_11N 0x6D8
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#define ODM_REG_ANT_TRAIN_PARA1_11N 0x7b0
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#define ODM_REG_ANT_TRAIN_PARA2_11N 0x7b4
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/* @DIG Related */
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#define ODM_BIT_IGI_11N 0x0000007F
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#define ODM_BIT_CCK_RPT_FORMAT_11N BIT(9)
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#define ODM_BIT_BB_RX_PATH_11N 0xF
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#define ODM_BIT_BB_TX_PATH_11N 0xF
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#define ODM_BIT_BB_ATC_11N BIT(11)
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@@ -804,7 +804,7 @@ typedef struct {
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__IO uint32_t RXDMA_AGG_PG_TH; /* 0x0280 RX DMA Aggregation Page Threshold */
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__IO uint32_t FW_UPD_RDPTR; /* 0x0284 Firmware Update Read Pointer */
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__IO uint16_t RXDMA_CONTROL; /* 0x0286 RX DMA Control */
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__I uint8_t RXPKT_NUM; /* 0x0287 RX Packet Number */
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__IO uint8_t RXPKT_NUM; /* 0x0287 RX Packet Number */
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__I uint32_t RXDMA_STATUS; /* 0x0288 RX DMA Status */
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uint8_t RESERVED1[4]; /* 0x028C-0x028F */
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__IO uint32_t RXDMA_PRO; /* 0x0290 RX DMA PRO */
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@@ -886,16 +886,6 @@ typedef struct {
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__IO uint32_t INT_MASK; /* 0x03E8 - Interrupt Mask */
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__I uint32_t INT_STATUS; /* 0x03EC - Interrupt Status */
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} WiFi_LXBUS_TypeDef;
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/* bits */
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#define LXBUS_CTRL_BIT8 (1 << 8) /* Control register bit 8 */
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#define LXBUS_K32_CTRL_BIT0 (1 << 0) /* 32K Control bit 0 */
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#define LXBUS_K32_CTRL_BIT6 (1 << 6) /* 32K Control bit 6 */
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#define LXBUS_K32_CTRL_BIT7 (1 << 7) /* 32K Control bit 7 */
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/* DMA config */
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#define LXBUS_DMA_CFG_TYPE1 0x1004 /* DMA config type 1 */
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#define LXBUS_DMA_CFG_TYPE2 0x2004 /* DMA config type 2 */
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#define LXBUS_DMA_CFG_TYPE3 0x1002 /* DMA config type 3 */
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/* 0x0400h ~ 0x047Fh Protocol Configuration */
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typedef struct {
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@@ -1498,4 +1488,757 @@ static inline void PINMUX_ConfigPadPull(uint8_t pin, uint8_t pull_type) {
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#define APBPeriph_FLASH BIT_SOC_FLASH_EN
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#define APBPeriph_LXBUS BIT_SOC_LXBUS_EN
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/* rtl8711b_wifi.h (it doesn't actually exist) :) */
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/* 8192C Cmd9346CR bits (Offset 0xA, 16bit) */
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#define CmdEEPROM_En (1 << 5) // EEPROM enable when set 1
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/* System EEPROM select, 0: boot from E-FUSE, 1: The EEPROM used is 9346 */
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#define CmdEERPOMSEL (1 << 4)
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#define Cmd9346CR_9356SEL (1 << 4)
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/* 8192C GPIO MUX Configuration Register (offset 0x40, 4 byte) */
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#define GPIOSEL_GPIO (1 << 0)
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#define GPIOSEL_ENBT (1 << 5)
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/* 8192C GPIO PIN Control Register (offset 0x44, 4 byte) */
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/* TODO: we don't have REG_GPIO_PIN_CTRL_8711? :^) */
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#define GPIO_VAL_IN REG_GPIO_PIN_CTRL_8711 // GPIO pins input value
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#define GPIO_VAL_OUT (REG_GPIO_PIN_CTRL_8711 + 1) // GPIO pins output value
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/* GPIO pins output enable when a bit is set to "1"; otherwise, input is
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* configured. */
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#define GPIO_IO_SEL (REG_GPIO_PIN_CTRL_8711 + 2)
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#define GPIO_MOD (REG_GPIO_PIN_CTRL_8711 + 3)
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#define HAL_8192C_HW_GPIO_WPS_BIT (1 << 2)
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/* 8723/8188E Host System Interrupt Mask Register (offset 0x58, 32 byte) */
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#define HSIMR_GPIO12_0_INT_EN (1 << 0)
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#define HSIMR_SPS_OCP_INT_EN (1 << 5)
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#define HSIMR_RON_INT_EN (1 << 6)
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#define HSIMR_PDN_INT_EN (1 << 7)
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#define HSIMR_GPIO9_INT_EN (1 << 25)
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/* 8723/8188E Host System Interrupt Status Register (offset 0x5C, 32 byte) */
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#define HSISR_GPIO12_0_INT (1 << 0)
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#define HSISR_SPS_OCP_INT (1 << 5)
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#define HSISR_RON_INT_EN (1 << 6)
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#define HSISR_PDNINT (1 << 7)
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#define HSISR_GPIO9_INT (1 << 25)
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/* 8192C (MSR) Media Status Register (Offset 0x4C, 8 bits) */
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/*
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Network Type
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00: No link
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01: Link in ad hoc network
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10: Link in infrastructure network
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11: AP mode
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Default: 00b.
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*/
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#define MSR_NOLINK 0x00
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#define MSR_ADHOC 0x01
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#define MSR_INFRA 0x02
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#define MSR_AP 0x03
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/* 88EU (MSR) Media Status Register (Offset 0x4C, 8 bits) */
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#define USB_INTR_CONTENT_HISR_OFFSET 48
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#define USB_INTR_CONTENT_HISRE_OFFSET 52
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/* 6. Adaptive Control Registers (Offset: 0x0160 - 0x01CF) */
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/* 8192C Response Rate Set Register (offset 0x181, 24bits) */
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#define RRSR_1M (1 << 0)
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#define RRSR_2M (1 << 1)
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#define RRSR_5_5M (1 << 2)
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#define RRSR_11M (1 << 3)
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#define RRSR_6M (1 << 4)
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#define RRSR_9M (1 << 5)
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#define RRSR_12M (1 << 6)
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#define RRSR_18M (1 << 7)
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#define RRSR_24M (1 << 8)
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#define RRSR_36M (1 << 9)
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#define RRSR_48M (1 << 10)
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#define RRSR_54M (1 << 11)
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#define RRSR_MCS0 (1 << 12)
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#define RRSR_MCS1 (1 << 13)
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#define RRSR_MCS2 (1 << 14)
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#define RRSR_MCS3 (1 << 15)
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#define RRSR_MCS4 (1 << 16)
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#define RRSR_MCS5 (1 << 17)
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#define RRSR_MCS6 (1 << 18)
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#define RRSR_MCS7 (1 << 19)
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/* 8192C Response Rate Set Register (offset 0x1BF, 8bits) */
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/* WOL bit information */
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#define HAL92C_WOL_PTK_UPDATE_EVENT (1 << 0)
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#define HAL92C_WOL_GTK_UPDATE_EVENT (1 << 1)
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/* 8192C Rate Definition */
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/* CCK */
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#define RATR_1M 0x00000001
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#define RATR_2M 0x00000002
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#define RATR_55M 0x00000004
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#define RATR_11M 0x00000008
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/* OFDM */
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#define RATR_6M 0x00000010
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#define RATR_9M 0x00000020
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#define RATR_12M 0x00000040
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#define RATR_18M 0x00000080
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#define RATR_24M 0x00000100
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#define RATR_36M 0x00000200
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#define RATR_48M 0x00000400
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#define RATR_54M 0x00000800
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/* MCS 1 Spatial Stream */
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#define RATR_MCS0 0x00001000
|
||||
#define RATR_MCS1 0x00002000
|
||||
#define RATR_MCS2 0x00004000
|
||||
#define RATR_MCS3 0x00008000
|
||||
#define RATR_MCS4 0x00010000
|
||||
#define RATR_MCS5 0x00020000
|
||||
#define RATR_MCS6 0x00040000
|
||||
#define RATR_MCS7 0x00080000
|
||||
/* MCS 2 Spatial Stream */
|
||||
#define RATR_MCS8 0x00100000
|
||||
#define RATR_MCS9 0x00200000
|
||||
#define RATR_MCS10 0x00400000
|
||||
#define RATR_MCS11 0x00800000
|
||||
#define RATR_MCS12 0x01000000
|
||||
#define RATR_MCS13 0x02000000
|
||||
#define RATR_MCS14 0x04000000
|
||||
#define RATR_MCS15 0x08000000
|
||||
|
||||
/* NOTE: For 92CU - Ziv */
|
||||
/* CCK */
|
||||
#define RATE_1M (1 << 0)
|
||||
#define RATE_2M (1 << 1)
|
||||
#define RATE_5_5M (1 << 2)
|
||||
#define RATE_11M (1 << 3)
|
||||
/* OFDM */
|
||||
#define RATE_6M (1 << 4)
|
||||
#define RATE_9M (1 << 5)
|
||||
#define RATE_12M (1 << 6)
|
||||
#define RATE_18M (1 << 7)
|
||||
#define RATE_24M (1 << 8)
|
||||
#define RATE_36M (1 << 9)
|
||||
#define RATE_48M (1 << 10)
|
||||
#define RATE_54M (1 << 11)
|
||||
/* MCS 1 Spatial Stream */
|
||||
#define RATE_MCS0 (1 << 12)
|
||||
#define RATE_MCS1 (1 << 13)
|
||||
#define RATE_MCS2 (1 << 14)
|
||||
#define RATE_MCS3 (1 << 15)
|
||||
#define RATE_MCS4 (1 << 16)
|
||||
#define RATE_MCS5 (1 << 17)
|
||||
#define RATE_MCS6 (1 << 18)
|
||||
#define RATE_MCS7 (1 << 19)
|
||||
/* MCS 2 Spatial Stream */
|
||||
#define RATE_MCS8 (1 << 20)
|
||||
#define RATE_MCS9 (1 << 21)
|
||||
#define RATE_MCS10 (1 << 22)
|
||||
#define RATE_MCS11 (1 << 23)
|
||||
#define RATE_MCS12 (1 << 24)
|
||||
#define RATE_MCS13 (1 << 25)
|
||||
#define RATE_MCS14 (1 << 26)
|
||||
#define RATE_MCS15 (1 << 27)
|
||||
|
||||
/* ALL CCK Rate */
|
||||
#define RATE_ALL_CCK RATR_1M | RATR_2M | RATR_55M | RATR_11M
|
||||
#define RATE_ALL_OFDM_AG \
|
||||
RATR_6M | RATR_9M | RATR_12M | RATR_18M | RATR_24M | RATR_36M | RATR_48M | \
|
||||
RATR_54M
|
||||
#define RATE_ALL_OFDM_1SS \
|
||||
RATR_MCS0 | RATR_MCS1 | RATR_MCS2 | RATR_MCS3 | RATR_MCS4 | RATR_MCS5 | \
|
||||
RATR_MCS6 | RATR_MCS7
|
||||
#define RATE_ALL_OFDM_2SS \
|
||||
RATR_MCS8 | RATR_MCS9 | RATR_MCS10 | RATR_MCS11 | RATR_MCS12 | RATR_MCS13 | \
|
||||
RATR_MCS14 | RATR_MCS15
|
||||
|
||||
#define RATE_BITMAP_ALL 0xFFFFF
|
||||
|
||||
/* Only use CCK 1M rate for ACK */
|
||||
#define RATE_RRSR_CCK_ONLY_1M 0xFFFF1
|
||||
|
||||
/* 8192C BW_OPMODE bits (Offset 0x203, 8bit) */
|
||||
#define BW_OPMODE_20MHZ (1 << 2)
|
||||
#define BW_OPMODE_5G (1 << 1)
|
||||
|
||||
/* 10. Power Save Control Registers (Offset: 0x0260 - 0x02DF) */
|
||||
#define WOW_PMEN (1 << 0) // Power management Enable.
|
||||
#define WOW_WOMEN (1 << 1) // WoW function on or off.
|
||||
#define WOW_MAGIC (1 << 2) // Magic packet
|
||||
#define WOW_UWF (1 << 3) // Unicast Wakeup frame.
|
||||
|
||||
/* 8711 IMR/ISR bits (offset 0x80, 8bits) */
|
||||
#if 0
|
||||
// The interrupt mask from WL page 1 interrupt source
|
||||
#define IMR_WL_FTINT_MSK_8711B (1 << 31)
|
||||
// P2P NoA RF off time indication interrupt mask
|
||||
#define IMR_P2P_RFOFF_INT_MSK_8711B (1 << 9)
|
||||
// P2P NoA RF on time indication interrupt mask
|
||||
#define IMR_P2P_RFON_INT_MSK_8711B (1 << 8)
|
||||
#define IMR_PSTIMER_MSK_8711B (1 << 6) // Enable PSTimer interrupt source
|
||||
#define IMR_TIMEOUT1_MSK_8711B (1 << 5) // Enable Timer1 interrupt source
|
||||
#define IMR_TIMEOUT0_MSK_8711B (1 << 4) // Enable Timer0 interrupt source
|
||||
// Enable MTI_BCNIVLEAR _INT
|
||||
// This interrupt is issued at the time set by DRVERLYINT register before TBTT time.
|
||||
#define IMR_MTI_BCNIVLEAR_INT_MSK_8711B (1 << 1)
|
||||
#define IMR_BCNERLY_MSK_8711B (1 << 0)
|
||||
#endif
|
||||
|
||||
#define IMR_MSK_CPWM2 (1 << 25)
|
||||
#define IMR_MSK_CPWM (1 << 24)
|
||||
/* "Rx packet buffer OverflowSet this bit to one when Rx packet buffer write
|
||||
* pointer hits read pointer." */
|
||||
#define IMR_FOVW_MSK_8711B (1 << 23)
|
||||
#define IMR_TXBCN0ERR_8711B (1 << 20) // Transmit Beacon0 Error
|
||||
#define IMR_TXBCN0OK_8711B (1 << 19) // Transmit Beacon0 OK
|
||||
|
||||
/* "Transmit packet buffer Overflow.This bit is set to 1 when one or more of the
|
||||
* hardware transmit queues is full" */
|
||||
#define IMR_TXFOVW_MSK_8711B (1 << 18)
|
||||
|
||||
/* Enable TSF_BIT32_TOGGLE interrupt source */
|
||||
#define IMR_TSF_BIT32_TOGGLE_MSK_V1_8711B (1 << 17)
|
||||
|
||||
/* This bit masks the CTWindow End interrupt. */
|
||||
#define IMR_CTWEndINT_MSK_8711B (1 << 13)
|
||||
|
||||
/* BCNDMA interrupt masks for 8711B
|
||||
* When BCNDMA interval arrives before TBTTx, these interrupts
|
||||
* inform MCU to prepare related beacon tasks.
|
||||
*/
|
||||
#define IMR_BCNDMA9_MSK_8711B (1 << 9)
|
||||
#define IMR_BCNDMA8_MSK_8711B (1 << 8)
|
||||
#define IMR_BCNDMA7_MSK_8711B (1 << 7)
|
||||
#define IMR_BCNDMA6_MSK_8711B (1 << 6)
|
||||
#define IMR_BCNDMA5_MSK_8711B (1 << 5)
|
||||
#define IMR_BCNDMA4_MSK_8711B (1 << 4)
|
||||
#define IMR_BCNDMA3_MSK_8711B (1 << 3)
|
||||
#define IMR_BCNDMA2_MSK_8711B (1 << 2)
|
||||
#define IMR_BCNDMA1_MSK_8711B (1 << 1)
|
||||
#define IMR_BCNDMA0_MSK_8711B (1 << 0)
|
||||
|
||||
#if 0
|
||||
/* 8711 IMR/ISR bits (offset 0x134, 8bits) */
|
||||
/* Be a beamformer, this interrupt is issued at the time after sounding finish */
|
||||
#define IMR_SOUND_DONE_MSK_8711B (1 << 30)
|
||||
/* When TRY_FINISH is deasserted, this interrupt is issued to inform MCU */
|
||||
#define IMR_TRY_DONE_MSK_8711B (1 << 29)
|
||||
#define IMR_TXRPT_CNT_FULL_MSK_8711B (1 << 28)
|
||||
#define IMR_WLACTOFF_INT_EN_8711B (1 << 27)
|
||||
#define IMR_WLACTON_INT_EN_8711B (1 << 26)
|
||||
#define IMR_TXPKTIN_INT_EN_8711B (1 << 25)
|
||||
#define IMR_RX_UMD0_EN_8711B (1 << 22)
|
||||
#define IMR_RX_UMD1_EN_8711B (1 << 21)
|
||||
#define IMR_RX_BMD0_EN_8711B (1 << 20)
|
||||
#define IMR_RX_BMD1_EN_8711B (1 << 19)
|
||||
#define IMR_BCN_RX_INT_EN_8711B (1 << 18)
|
||||
#define IMR_TBTTINT_MSK_8711B (1 << 17)
|
||||
|
||||
#define IMR_STBY_MSK_8711B (1 << 7) // Lower Power Standby Interrupt mask
|
||||
#define IMR_RXDONE_MSK_8711B (1 << 3) // Rx Packet done for 8051
|
||||
/* FWHW/ TXDMA/ RXDMA/ WMAC error status interrupt */
|
||||
#define IMR_ERRORHDL_MSK_8711B (1 << 2)
|
||||
/* CCX PKT TX Report Interrupt */
|
||||
#define IMR_TXCCX_MSK_FW_8711B (1 << 1)
|
||||
/* TX Finish (Ack/BA process Finish) Interrupt. */
|
||||
#define IMR_TXCLOSE_MSK_8711B (1 << 0)
|
||||
|
||||
#endif
|
||||
|
||||
/* 8711 IMR/ISR bits (offset 0x13C, 8bits) */
|
||||
#define IMR_TXBCN1ERR_8711B (1 << 15) // Transmit Beacon1 Error
|
||||
#define IMR_TXBCN1OK_8711B (1 << 14) // Transmit Beacon1 OK
|
||||
|
||||
/* 8711 IMR/ISR bits offset 0x3EC, 8bits) */
|
||||
#define IMR_BCNDERR7_8711B (1 << 31) // Beacon Queue DMA Error
|
||||
#define IMR_BCNDERR6_8711B (1 << 30) // Beacon Queue DMA Error
|
||||
#define IMR_BCNDERR5_8711B (1 << 29) // Beacon Queue DMA Error
|
||||
#define IMR_BCNDERR4_8711B (1 << 28) // Beacon Queue DMA Error
|
||||
#define IMR_BCNDERR3_8711B (1 << 27) // Beacon Queue DMA Error
|
||||
#define IMR_BCNDERR2_8711B (1 << 26) // Beacon Queue DMA Error
|
||||
#define IMR_BCNDERR1_8711B (1 << 25) // Beacon Queue DMA Error
|
||||
#define IMR_BCNDERR0_8711B (1 << 24) // Beacon Queue DMA Error
|
||||
#define IMR_BCNDMAOK7_8711B (1 << 23) // Beacon DMA OK Interrupt 7
|
||||
#define IMR_BCNDMAOK6_8711B (1 << 22) // Beacon DMA OK Interrupt 6
|
||||
#define IMR_BCNDMAOK5_8711B (1 << 21) // Beacon DMA OK Interrupt 5
|
||||
#define IMR_BCNDMAOK4_8711B (1 << 20) // Beacon DMA OK Interrupt 4
|
||||
#define IMR_BCNDMAOK3_8711B (1 << 19) // Beacon DMA OK Interrupt 3
|
||||
#define IMR_BCNDMAOK2_8711B (1 << 18) // Beacon DMA OK Interrupt 2
|
||||
#define IMR_BCNDMAOK1_8711B (1 << 17) // Beacon DMA OK Interrupt 1
|
||||
#define IMR_BCNDMAOK0_8711B (1 << 16) // Beacon DMA OK Interrupt 0
|
||||
#define IMR_H7DOK_8711B (1 << 15) // High Queue DMA OK Interrup 7
|
||||
#define IMR_H6DOK_8711B (1 << 14) // High Queue DMA OK Interrup 6
|
||||
#define IMR_H5DOK_8711B (1 << 13) // High Queue DMA OK Interrup 5
|
||||
#define IMR_H4DOK_8711B (1 << 12) // High Queue DMA OK Interrup 4
|
||||
#define IMR_H3DOK_8711B (1 << 11) // High Queue DMA OK Interrup 3
|
||||
#define IMR_H2DOK_8711B (1 << 10) // High Queue DMA OK Interrup 2
|
||||
#define IMR_H1DOK_8711B (1 << 9) // High Queue DMA OK Interrup 1
|
||||
#define IMR_H0DOK_8711B (1 << 8) // High Queue DMA OK Interrup 1
|
||||
#define IMR_MGNTDOK_8711B (1 << 6) // Management Queue DMA OK
|
||||
#define IMR_BKDOK_8711B (1 << 5) // AC_BK DMA OK
|
||||
#define IMR_BEDOK_8711B (1 << 4) // AC_BE DMA OK
|
||||
#define IMR_VIDOK_8711B (1 << 3) // AC_VI DMA OK
|
||||
#define IMR_VODOK_8711B (1 << 2) // AC_VO DMA OK
|
||||
#define IMR_RDU_8711B (1 << 1) // Rx Descriptor Unavailable
|
||||
#define IMR_ROK_8711B (1 << 0) // Receive DMA OK
|
||||
|
||||
/*===================================================================
|
||||
=====================================================================
|
||||
Here the register defines are for 92C. When the define is as same with 92C,
|
||||
we will use the 92C's define for the consistency
|
||||
So the following defines for 92C is not entire!!!!!!
|
||||
=====================================================================
|
||||
=====================================================================*/
|
||||
/*
|
||||
* Based on Datasheet V33---090401
|
||||
* Register Summary
|
||||
* Current IOREG MAP
|
||||
* 0x0000h ~ 0x00FFh System Configuration (256 Bytes)
|
||||
* 0x0100h ~ 0x01FFh MACTOP General Configuration (256 Bytes)
|
||||
* 0x0200h ~ 0x027Fh TXDMA Configuration (128 Bytes)
|
||||
* 0x0280h ~ 0x02FFh RXDMA Configuration (128 Bytes)
|
||||
* 0x0300h ~ 0x03FFh PCIE EMAC Reserved Region (256 Bytes)
|
||||
* 0x0400h ~ 0x04FFh Protocol Configuration (256 Bytes)
|
||||
* 0x0500h ~ 0x05FFh EDCA Configuration (256 Bytes)
|
||||
* 0x0600h ~ 0x07FFh WMAC Configuration (512 Bytes)
|
||||
* 0x2000h ~ 0x3FFFh 8051 FW Download Region (8196 Bytes)
|
||||
*/
|
||||
|
||||
/* 8711 (TXPAUSE) transmission pause (Offset 0x522, 8 bits) */
|
||||
#define StopBecon (1 << 6)
|
||||
#define StopHigh (1 << 5)
|
||||
#define StopMgt (1 << 4)
|
||||
#define StopVO (1 << 3)
|
||||
#define StopVI (1 << 2)
|
||||
#define StopBE (1 << 1)
|
||||
#define StopBK (1 << 0)
|
||||
|
||||
/* 8192C Regsiter Bit and Content definition */
|
||||
/* 0x0000h ~ 0x00FFh System Configuration */
|
||||
/* 2 SYS_ISO_CTRL */
|
||||
#define ISO_MD2PP (1 << 0)
|
||||
#define ISO_UA2USB (1 << 1)
|
||||
#define ISO_UD2CORE (1 << 2)
|
||||
#define ISO_PA2PCIE (1 << 3)
|
||||
#define ISO_PD2CORE (1 << 4)
|
||||
#define ISO_IP2MAC (1 << 5)
|
||||
#define ISO_DIOP (1 << 6)
|
||||
#define ISO_DIOE (1 << 7)
|
||||
#define ISO_EB2CORE (1 << 8)
|
||||
#define ISO_DIOR (1 << 9)
|
||||
#define PWC_EV12V (1 << 15)
|
||||
|
||||
/* 2 SYS_FUNC_EN */
|
||||
#define FEN_BBRSTB (1 << 0)
|
||||
#define FEN_BB_GLB_RSTn (1 << 1)
|
||||
#define FEN_USBA (1 << 2)
|
||||
#define FEN_UPLL (1 << 3)
|
||||
#define FEN_USBD (1 << 4)
|
||||
#define FEN_DIO_PCIE (1 << 5)
|
||||
#define FEN_PCIEA (1 << 6)
|
||||
#define FEN_PPLL (1 << 7)
|
||||
#define FEN_PCIED (1 << 8)
|
||||
#define FEN_DIOE (1 << 9)
|
||||
#define FEN_CPUEN (1 << 10)
|
||||
#define FEN_DCORE (1 << 11)
|
||||
#define FEN_ELDR (1 << 12)
|
||||
#define FEN_DIO_RF (1 << 13)
|
||||
#define FEN_HWPDN (1 << 14)
|
||||
#define FEN_MREGEN (1 << 15)
|
||||
|
||||
/* 2 APS_FSMCO */
|
||||
#define PFM_LDALL (1 << 0)
|
||||
#define PFM_ALDN (1 << 1)
|
||||
#define PFM_LDKP (1 << 2)
|
||||
#define PFM_WOWL (1 << 3)
|
||||
#define EnPDN (1 << 4)
|
||||
#define PDN_PL (1 << 5)
|
||||
#define APFM_ONMAC (1 << 8)
|
||||
#define APFM_OFF (1 << 9)
|
||||
#define APFM_RSM (1 << 10)
|
||||
#define AFSM_HSUS (1 << 11)
|
||||
#define AFSM_PCIE (1 << 12)
|
||||
#define APDM_MAC (1 << 13)
|
||||
#define APDM_HOST (1 << 14)
|
||||
#define APDM_HPDN (1 << 15)
|
||||
#define RDY_MACON (1 << 16)
|
||||
#define SUS_HOST (1 << 17)
|
||||
#define ROP_ALD (1 << 20)
|
||||
#define ROP_PWR (1 << 21)
|
||||
#define ROP_SPS (1 << 22)
|
||||
#define SOP_MRST (1 << 25)
|
||||
#define SOP_FUSE (1 << 26)
|
||||
#define SOP_ABG (1 << 27)
|
||||
#define SOP_AMB (1 << 28)
|
||||
#define SOP_RCK (1 << 29)
|
||||
#define SOP_A8M (1 << 30)
|
||||
#define XOP_BTCK (1 << 31)
|
||||
|
||||
/* 2 SYS_CLKR */
|
||||
#define ANAD16V_EN (1 << 0)
|
||||
#define ANA8M (1 << 1)
|
||||
#define MACSLP (1 << 4)
|
||||
#define LOADER_CLK_EN (1 << 5)
|
||||
|
||||
/* 2 9346CR */
|
||||
|
||||
#define BOOT_FROM_EEPROM (1 << 4)
|
||||
#define EEPROM_EN (1 << 5)
|
||||
|
||||
/* 2 RF_CTRL */
|
||||
#define RF_EN (1 << 0)
|
||||
#define RF_RSTB (1 << 1)
|
||||
#define RF_SDMRSTB (1 << 2)
|
||||
|
||||
/* 2 LDOV12D_CTRL */
|
||||
#define LDV12_EN (1 << 0)
|
||||
#define LDV12_SDBY (1 << 1)
|
||||
#define LPLDO_HSM (1 << 2)
|
||||
#define LPLDO_LSM_DIS (1 << 3)
|
||||
#define _LDV12_VADJ(x) (((x) & 0xF) << 4)
|
||||
|
||||
/* 2 EFUSE_TEST (For RTL8723 partially) */
|
||||
#define EF_TRPT (1 << 7)
|
||||
/* 00: Wifi Efuse, 01: BT Efuse0, 10: BT Efuse1, 11: BT Efuse2 */
|
||||
#define EF_CELL_SEL ((1 << 8) | (1 << 9))
|
||||
#define LDOE25_EN (1 << 31)
|
||||
#define EFUSE_SEL(x) (((x) & 0x3) << 8)
|
||||
#define EFUSE_SEL_MASK 0x300
|
||||
#define EFUSE_WIFI_SEL_0 0x0
|
||||
#define EFUSE_BT_SEL_0 0x1
|
||||
#define EFUSE_BT_SEL_1 0x2
|
||||
#define EFUSE_BT_SEL_2 0x3
|
||||
|
||||
/* 2 8051FWDL */
|
||||
/* 2 MCUFWDL */
|
||||
#define MCUFWDL_EN (1 << 0)
|
||||
#define MCUFWDL_RDY (1 << 1)
|
||||
#define FWDL_ChkSum_rpt (1 << 2)
|
||||
#define MACINI_RDY (1 << 3)
|
||||
#define BBINI_RDY (1 << 4)
|
||||
#define RFINI_RDY (1 << 5)
|
||||
#define WINTINI_RDY (1 << 6)
|
||||
#define RAM_DL_SEL (1 << 7)
|
||||
#define ROM_DLEN (1 << 19)
|
||||
#define CPRST (1 << 23)
|
||||
|
||||
/* 2 REG_SYS_CFG */
|
||||
#define XCLK_VLD (1 << 0)
|
||||
#define ACLK_VLD (1 << 1)
|
||||
#define UCLK_VLD (1 << 2)
|
||||
#define PCLK_VLD (1 << 3)
|
||||
#define PCIRSTB (1 << 4)
|
||||
#define V15_VLD (1 << 5)
|
||||
#define TRP_B15V_EN (1 << 7)
|
||||
#define SIC_IDLE (1 << 8)
|
||||
#define BD_MAC2 (1 << 9)
|
||||
#define BD_MAC1 (1 << 10)
|
||||
#define IC_MACPHY_MODE (1 << 11)
|
||||
#define CHIP_VER ((1 << 12) | (1 << 13) | (1 << 14) | (1 << 15))
|
||||
#define BT_FUNC (1 << 16)
|
||||
#define VENDOR_ID (1 << 19)
|
||||
#define PAD_HWPD_IDN (1 << 22)
|
||||
#define TRP_VAUX_EN (1 << 23) /* RTL ID */
|
||||
#define TRP_BT_EN (1 << 24)
|
||||
#define BD_PKG_SEL (1 << 25)
|
||||
#define BD_HCI_SEL (1 << 26)
|
||||
#define TYPE_ID (1 << 27)
|
||||
|
||||
#define CHIP_VER_RTL_MASK 0xF000 /* Bit 12 ~ 15 */
|
||||
#define CHIP_VER_RTL_SHIFT 12
|
||||
|
||||
/* 0x0100h ~ 0x01FFh MACTOP General Configuration */
|
||||
|
||||
/* 2 Function Enable Registers */
|
||||
/* 2 CR 0x0100-0x0103 */
|
||||
#define HCI_TXDMA_EN (1 << 0)
|
||||
#define HCI_RXDMA_EN (1 << 1)
|
||||
#define TXDMA_EN (1 << 2)
|
||||
#define RXDMA_EN (1 << 3)
|
||||
#define PROTOCOL_EN (1 << 4)
|
||||
#define SCHEDULE_EN (1 << 5)
|
||||
#define MACTXEN (1 << 6)
|
||||
#define MACRXEN (1 << 7)
|
||||
#define ENSWBCN (1 << 8)
|
||||
#define ENSEC (1 << 9)
|
||||
#define CALTMR_EN (1 << 10) /* 32k CAL TMR enable */
|
||||
|
||||
/* Network type */
|
||||
#define _NETTYPE(x) (((x) & 0x3) << 16)
|
||||
#define MASK_NETTYPE 0x30000
|
||||
#define NT_NO_LINK 0x0
|
||||
#define NT_LINK_AD_HOC 0x1
|
||||
#define NT_LINK_AP 0x2
|
||||
#define NT_AS_AP 0x3
|
||||
|
||||
/* 2 PBP - Page Size Register 0x0104 */
|
||||
#define GET_RX_PAGE_SIZE(value) ((value) & 0xF)
|
||||
#define GET_TX_PAGE_SIZE(value) (((value) & 0xF0) >> 4)
|
||||
#define _PSRX_MASK 0xF
|
||||
#define _PSTX_MASK 0xF0
|
||||
#define _PSRX(x) (x)
|
||||
#define _PSTX(x) ((x) << 4)
|
||||
|
||||
#define PBP_64 0x0
|
||||
#define PBP_128 0x1
|
||||
#define PBP_256 0x2
|
||||
#define PBP_512 0x3
|
||||
#define PBP_1024 0x4
|
||||
|
||||
/* 2 TX/RXDMA 0x010C */
|
||||
#define RXDMA_ARBBW_EN (1 << 0)
|
||||
#define RXSHFT_EN (1 << 1)
|
||||
#define RXDMA_AGG_EN (1 << 2)
|
||||
#define QS_VO_QUEUE (1 << 8)
|
||||
#define QS_VI_QUEUE (1 << 9)
|
||||
#define QS_BE_QUEUE (1 << 10)
|
||||
#define QS_BK_QUEUE (1 << 11)
|
||||
#define QS_MANAGER_QUEUE (1 << 12)
|
||||
#define QS_HIGH_QUEUE (1 << 13)
|
||||
|
||||
#define HQSEL_VOQ (1 << 0)
|
||||
#define HQSEL_VIQ (1 << 1)
|
||||
#define HQSEL_BEQ (1 << 2)
|
||||
#define HQSEL_BKQ (1 << 3)
|
||||
#define HQSEL_MGTQ (1 << 4)
|
||||
#define HQSEL_HIQ (1 << 5)
|
||||
|
||||
/* For normal driver, 0x10C */
|
||||
#define _TXDMA_HIQ_MAP(x) (((x) & 0x3) << 14)
|
||||
#define _TXDMA_MGQ_MAP(x) (((x) & 0x3) << 12)
|
||||
#define _TXDMA_BKQ_MAP(x) (((x) & 0x3) << 10)
|
||||
#define _TXDMA_BEQ_MAP(x) (((x) & 0x3) << 8)
|
||||
#define _TXDMA_VIQ_MAP(x) (((x) & 0x3) << 6)
|
||||
#define _TXDMA_VOQ_MAP(x) (((x) & 0x3) << 4)
|
||||
|
||||
#define QUEUE_LOW 1
|
||||
#define QUEUE_NORMAL 2
|
||||
#define QUEUE_HIGH 3
|
||||
|
||||
/* 2 REG_C2HEVT_CLEAR 0x01AF */
|
||||
/* Set by driver and notify FW that the driver has read the C2H command message
|
||||
*/
|
||||
#define C2H_EVT_HOST_CLOSE 0x00
|
||||
/* Set by FW indicating that FW had set the C2H command message and it's not yet
|
||||
* read by driver. */
|
||||
#define C2H_EVT_FW_CLOSE 0xFF
|
||||
|
||||
/* 2 LLT_INIT 0x01E0 */
|
||||
#define _LLT_NO_ACTIVE 0x0
|
||||
#define _LLT_WRITE_ACCESS 0x1
|
||||
#define _LLT_READ_ACCESS 0x2
|
||||
|
||||
#define _LLT_INIT_DATA(x) ((x) & 0xFF)
|
||||
#define _LLT_INIT_ADDR(x) (((x) & 0xFF) << 8)
|
||||
#define _LLT_OP(x) (((x) & 0x3) << 30)
|
||||
#define _LLT_OP_VALUE(x) (((x) >> 30) & 0x3)
|
||||
|
||||
/* 0x0200h ~ 0x027Fh TXDMA Configuration */
|
||||
/* 2 TDECTL 0x0208 */
|
||||
#define BLK_DESC_NUM_SHIFT 4
|
||||
#define BLK_DESC_NUM_MASK 0xF
|
||||
|
||||
/* 2 TXDMA_OFFSET_CHK 0x020C */
|
||||
#define DROP_DATA_EN (1 << 9)
|
||||
|
||||
/* 0x0280h ~ 0x028Bh RX DMA Configuration */
|
||||
/* REG_RXDMA_CONTROL, 0x0286h */
|
||||
/**
|
||||
* 2 REG_RXPKT_NUM, 0x0284
|
||||
* Write only. When this bit is set, RXDMA will decrease RX PKT counter by one.
|
||||
* Before this bit is polled, FW shall update RXFF_RD_PTR first. This register
|
||||
* is write pulse and auto clear.
|
||||
*/
|
||||
#define RXPKT_RELEASE_POLL (1 << 0)
|
||||
/**
|
||||
* Read only. When RXMA finishes on-going DMA operation, RXMDA will report idle
|
||||
* state in this bit. FW can start releasing packets after RXDMA entering idle
|
||||
* mode.
|
||||
*/
|
||||
#define RXDMA_IDLE (1 << 1)
|
||||
/**
|
||||
*
|
||||
* When this bit is set, RXDMA will enter this mode after on-going RXDMA packet
|
||||
* to host completed, and stop DMA packet to host. RXDMA will then report
|
||||
* Default: 0;
|
||||
*/
|
||||
#define RW_RELEASE_EN (1 << 2)
|
||||
|
||||
/* 0x0300h ~ 0x03FFh LxBUS Registers */
|
||||
/* some bit settings */
|
||||
#define LXBUS_CTRL_BIT8 (1 << 8) /* Control register bit 8 */
|
||||
#define LXBUS_K32_CTRL_BIT0 (1 << 0) /* 32K Control bit 0 */
|
||||
#define LXBUS_K32_CTRL_BIT6 (1 << 6) /* 32K Control bit 6 */
|
||||
#define LXBUS_K32_CTRL_BIT7 (1 << 7) /* 32K Control bit 7 */
|
||||
|
||||
/* DMA config */
|
||||
#define LXBUS_DMA_CFG_TYPE1 0x1004 /* DMA config type 1 */
|
||||
#define LXBUS_DMA_CFG_TYPE2 0x2004 /* DMA config type 2 */
|
||||
#define LXBUS_DMA_CFG_TYPE3 0x1002 /* DMA config type 3 */
|
||||
|
||||
/* 0x0400h ~ 0x047Fh Protocol Configuration */
|
||||
/* 2 FWHW_TXQ_CTRL 0x0420 */
|
||||
#define EN_AMPDU_RTY_NEW (1 << 7)
|
||||
|
||||
/* 2 REG_LIFECTRL_CTRL 0x0426 */
|
||||
#define HAL92C_EN_PKT_LIFE_TIME_BK (1 << 3)
|
||||
#define HAL92C_EN_PKT_LIFE_TIME_BE (1 << 2)
|
||||
#define HAL92C_EN_PKT_LIFE_TIME_VI (1 << 1)
|
||||
#define HAL92C_EN_PKT_LIFE_TIME_VO (1 << 0)
|
||||
|
||||
#define HAL92C_MSDU_LIFE_TIME_UNIT 128 // in us, said by Tim.
|
||||
|
||||
/* 2 SPEC SIFS 0x0428 */
|
||||
#define _SPEC_SIFS_CCK(x) ((x) & 0xFF)
|
||||
#define _SPEC_SIFS_OFDM(x) (((x) & 0xFF) << 8)
|
||||
|
||||
/* 2 RL 0x042A */
|
||||
#define RETRY_LIMIT_SHORT_SHIFT 8
|
||||
#define RETRY_LIMIT_LONG_SHIFT 0
|
||||
|
||||
#define _LRL(x) ((x) & 0x3F)
|
||||
#define _SRL(x) (((x) & 0x3F) << 8)
|
||||
|
||||
/* 0x0500h ~ 0x05FFh EDCA Configuration */
|
||||
/* 2 EDCA setting 0x050C */
|
||||
#define AC_PARAM_TXOP_LIMIT_OFFSET 16
|
||||
#define AC_PARAM_ECW_MAX_OFFSET 12
|
||||
#define AC_PARAM_ECW_MIN_OFFSET 8
|
||||
#define AC_PARAM_AIFS_OFFSET 0
|
||||
|
||||
/* 2 BCN_CTRL 0x0550 */
|
||||
#define EN_TXBCN_RPT (1 << 2)
|
||||
#define EN_BCN_FUNCTION (1 << 3)
|
||||
|
||||
/* 2 TxPause 0x0522 */
|
||||
#define STOP_BCNQ (1 << 6)
|
||||
|
||||
/* 2 ACMHWCTRL 0x05C0 */
|
||||
#define AcmHw_HwEn_8723B (1 << 0)
|
||||
#define AcmHw_VoqEn_8723B (1 << 1)
|
||||
#define AcmHw_ViqEn_8723B (1 << 2)
|
||||
#define AcmHw_BeqEn_8723B (1 << 3)
|
||||
#define AcmHw_VoqStatus_8723B (1 << 5)
|
||||
#define AcmHw_ViqStatus_8723B (1 << 6)
|
||||
#define AcmHw_BeqStatus_8723B (1 << 7)
|
||||
|
||||
/* 0x0600h ~ 0x07FFh WMAC Configuration */
|
||||
/* 2 TCR 0x0604 */
|
||||
#define DIS_GCLK (1 << 1)
|
||||
#define PAD_SEL (1 << 2)
|
||||
#define PWR_ST (1 << 6)
|
||||
#define PWRBIT_OW_EN (1 << 7)
|
||||
#define ACRC (1 << 8)
|
||||
#define CFENDFORM (1 << 9)
|
||||
#define ICV (1 << 10)
|
||||
|
||||
/* 8711 (RCR) Receive Configuration Register (Offset 0x608, 32 bits) */
|
||||
/* WMAC append FCS after payload */
|
||||
#define RCR_APPFCS (1 << 31)
|
||||
/* MACRX will retain the MIC at the bottom of the packet */
|
||||
#define RCR_APP_MIC (1 << 30) //
|
||||
/* MACRX will retain the ICV at the bottom of the packet. */
|
||||
#define RCR_APP_ICV (1 << 29)
|
||||
/* HY Status is appended before RX packet in RXFF */
|
||||
#define RCR_APP_PHYST_RXFF (1 << 28)
|
||||
/* SSN of previous TXBA is appended as after original RXDESC as the 4th DW of
|
||||
* RXDESC */
|
||||
#define RCR_APP_BA_SSN (1 << 27)
|
||||
#define RCR_RSVD_BIT26 (1 << 26) // Reserved
|
||||
#define RCR_TCPOFLD_EN (1 << 25) // Enable TCP checksum offload
|
||||
/* Enable Multiple BssId. Only response ACK to the packets whose DID(A1)
|
||||
* matching to the addresses in the MBSSID CAM Entries. */
|
||||
#define RCR_ENMBID (1 << 24)
|
||||
/* Enable LSIG TXOP Protection function. Search KEYCAM for each rx packet to
|
||||
* check if LSIGEN bit is set. */
|
||||
#define RCR_LSIGEN (1 << 23)
|
||||
/* Enable immediate MCS Feedback function. When Rx packet with MRQ = 1'b1, then
|
||||
* search KEYCAM to find sender's MCS Feedback function and send response. */
|
||||
#define RCR_MFBEN (1 << 22)
|
||||
/* WMAC clock stop and reset after BB transmitting end; 0: enable, 1: disable */
|
||||
#define RCR_MAC_RESET (1 << 19)
|
||||
#define RCR_TIM_PARSER_EN (1 << 18) // RX Beacon TIM Parser.
|
||||
#define RCR_BM_DATA_EN (1 << 17) // Broadcast data packet interrupt enable.
|
||||
#define RCR_UC_DATA_EN (1 << 16) // Unicast data packet interrupt enable.
|
||||
|
||||
#define RCR_HTC_LOC_CTRL (1 << 14) // MFC<--HTC=1 MFC-->HTC=0
|
||||
/* Accept management type frame */
|
||||
#define RCR_AMF (1 << 13)
|
||||
/* // Accept control type frame. Control frames BA, BAR, and PS-Poll
|
||||
* (when in AP mode) are not controlled by this bit. They are controlled by ADF.
|
||||
*/
|
||||
#define RCR_ACF (1 << 12)
|
||||
/* Accept data type frame. This bit also regulates BA, BAR, and PS-Poll (AP mode
|
||||
* only). */
|
||||
#define RCR_ADF (1 << 11)
|
||||
/* Accept ICV error packet */
|
||||
#define RCR_AICV (1 << 9)
|
||||
/* Accept CRC32 error packet */
|
||||
#define RCR_ACRC32 (1 << 8)
|
||||
/* Accept BSSID match packet (Rx beacon, probe rsp) */
|
||||
#define RCR_CBSSID_BCN (1 << 7)
|
||||
#define RCR_CBSSID_DATA (1 << 6) // Accept BSSID match packet (Data)
|
||||
#define RCR_CBSSID RCR_CBSSID_DATA // Accept BSSID match packet
|
||||
#define RCR_APWRMGT (1 << 5) // Accept power management packet
|
||||
#define RCR_ADD3 (1 << 4) // Accept address 3 match packet
|
||||
#define RCR_AB (1 << 3) // Accept broadcast packet
|
||||
#define RCR_AM (1 << 2) // Accept multicast packet
|
||||
#define RCR_APM (1 << 1) // Accept physical match packet
|
||||
#define RCR_AAP (1 << 0) // Accept all unicast packet
|
||||
|
||||
#define AAP (1 << 0)
|
||||
#define APM (1 << 1)
|
||||
#define AM (1 << 2)
|
||||
#define AB (1 << 3)
|
||||
#define ADD3 (1 << 4)
|
||||
#define APWRMGT (1 << 5)
|
||||
#define CBSSID (1 << 6)
|
||||
#define CBSSID_DATA (1 << 6)
|
||||
#define CBSSID_BCN (1 << 7)
|
||||
#define ACRC32 (1 << 8)
|
||||
#define AICV (1 << 9)
|
||||
#define ADF (1 << 11)
|
||||
#define ACF (1 << 12)
|
||||
#define AMF (1 << 13)
|
||||
#define HTC_LOC_CTRL (1 << 14)
|
||||
#define UC_DATA_EN (1 << 16)
|
||||
#define BM_DATA_EN (1 << 17)
|
||||
#define MFBEN (1 << 22)
|
||||
#define LSIGEN (1 << 23)
|
||||
#define EnMBID (1 << 24)
|
||||
#define APP_BASSN (1 << 27)
|
||||
#define APP_PHYSTS (1 << 28)
|
||||
#define APP_ICV (1 << 29)
|
||||
#define APP_MIC (1 << 30)
|
||||
|
||||
/* 8711 CAM Config Setting (offset 0x680, 1 byte) */
|
||||
#define SCR_TxUseDK (1 << 0) // Force Tx Use Default Key
|
||||
#define SCR_RxUseDK (1 << 1) // Force Rx Use Default Key
|
||||
#define SCR_TxEncEnable (1 << 2) // Enable Tx Encryption
|
||||
#define SCR_RxDecEnable (1 << 3) // Enable Rx Decryption
|
||||
#define SCR_SKByA2 (1 << 4) // Search kEY BY A2
|
||||
#define SCR_NoSKMC (1 << 5) // No Key Search Multicast
|
||||
#define SCR_TXBCUSEDK (1 << 6) // Force Tx Broadcast packets Use Default Key
|
||||
#define SCR_RXBCUSEDK (1 << 7) // Force Rx Broadcast packets Use Default Key
|
||||
|
||||
#define CAM_NONE 0x0
|
||||
#define CAM_WEP40 0x01
|
||||
#define CAM_TKIP 0x02
|
||||
#define CAM_AES 0x04
|
||||
#define CAM_WEP104 0x05
|
||||
#define CAM_SMS4 0x6
|
||||
|
||||
#define TOTAL_CAM_ENTRY 32
|
||||
#define HALF_CAM_ENTRY 16
|
||||
|
||||
#define CAM_CONFIG_USEDK TRUE
|
||||
#define CAM_CONFIG_NO_USEDK FALSE
|
||||
|
||||
#define SCR_UseDK 0x01
|
||||
#define SCR_TxSecEnable 0x02
|
||||
#define SCR_RxSecEnable 0x04
|
||||
|
||||
/* 8711 REG_BCN_PSR_RPT (Beacon Parser Report Register) (Offset 0x6A8, 32 bits)
|
||||
*/
|
||||
#define PS_TIM (1 << 14)
|
||||
#define PS_DTIM (1 << 15)
|
||||
|
||||
#endif
|
||||
|
||||
261
src/main.c
261
src/main.c
@@ -1,39 +1,258 @@
|
||||
#include <stdint.h>
|
||||
#include <strings.h>
|
||||
|
||||
#include "rtl8710bx.h"
|
||||
|
||||
extern uint32_t DiagPrintf(const char *fmt, ...)
|
||||
__attribute__((format(printf, 1, 2)));
|
||||
extern void DelayMs(uint32_t ms);
|
||||
|
||||
#define printf DiagPrintf
|
||||
|
||||
static inline void delay_cycles(unsigned int count) {
|
||||
__asm volatile(
|
||||
"1: \n"
|
||||
" subs %[count], %[count], #1 \n"
|
||||
" bne 1b \n"
|
||||
: [count] "+r"(count)
|
||||
:
|
||||
: "cc");
|
||||
typedef struct {
|
||||
char ssid[33];
|
||||
uint8_t bssid[6];
|
||||
uint8_t channel;
|
||||
int8_t rssi;
|
||||
} Network_Info_t;
|
||||
|
||||
static void wifi_init(void) {
|
||||
PERI_ON->PESOC_CLK_CTRL |=
|
||||
BIT_SOC_ACTCK_BTCMD_EN | BIT_SOC_ACTCK_VENDOR_REG_EN;
|
||||
PERI_ON->SOC_HCI_COM_FUNC_EN |= BIT_SOC_HCI_WL_MACON_EN;
|
||||
|
||||
WIFI->SYS.FUNC_EN |= FEN_MREGEN;
|
||||
WIFI->SYS.APS_FSMCO |= APFM_ONMAC;
|
||||
WIFI->SYS.APS_FSMCO &= ~SUS_HOST;
|
||||
WIFI->SYS.ISO_CTRL &= ~PWC_EV12V;
|
||||
|
||||
// printf("waiting for APS_FSMCO\n");
|
||||
// while (!(wifi->SYS.APS_FSMCO & RDY_MACON));
|
||||
// printf("RDY_MACON\n");
|
||||
|
||||
WIFI->WMAC.RCR |= (BM_DATA_EN | UC_DATA_EN); // broadcast, unicast
|
||||
WIFI->MAC.CR |= MACRXEN; // en RX
|
||||
}
|
||||
static inline void delay_ms(unsigned int ms) {
|
||||
for (unsigned int i = 0; i < ms; i++) {
|
||||
delay_cycles(15625); // 62500/4 cycles
|
||||
|
||||
void print_wifi_version(void) {
|
||||
printf("SYSTEM_CFG0 address: 0x%08X\n", (uint32_t)&SYSTEM_CTRL->SYSTEM_CFG0);
|
||||
printf("SYSTEM_CFG0: 0x%08X\n", SYSTEM_CTRL->SYSTEM_CFG0);
|
||||
// printf("SYSTEM_CFG1 address: 0x%08X\n",
|
||||
// (uint32_t)&SYSTEM_CTRL->SYSTEM_CFG1); printf("SYSTEM_CFG1: 0x%08X\n",
|
||||
// SYSTEM_CTRL->SYSTEM_CFG1); printf("SYSTEM_CFG2 address: 0x%08X\n",
|
||||
// (uint32_t)&SYSTEM_CTRL->SYSTEM_CFG2); printf("SYSTEM_CFG2: 0x%08X\n",
|
||||
// SYSTEM_CTRL->SYSTEM_CFG2);
|
||||
|
||||
// uint32_t xtal_type = ((cfg ^ 0x10000) >> 16) & 1;
|
||||
// uint32_t cut_id = (cfg >> 8) & 3;
|
||||
// uint32_t chip_id = (cfg >> 4) & 0xF;
|
||||
// uint32_t revision;
|
||||
|
||||
// if (cut_id == 1)
|
||||
// revision = 2;
|
||||
// else if (cut_id == 2)
|
||||
// revision = 1;
|
||||
// else
|
||||
// revision = 0;
|
||||
|
||||
// printf("SYSCFG0: 0x%08X\n", cfg);
|
||||
// printf("Version: 11\n");
|
||||
// printf("XTAL Type: 0x%x\n", xtal_type);
|
||||
// printf("Chip ID: 0x%x\n", chip_id);
|
||||
// printf("Revision: 0x%x\n", revision);
|
||||
}
|
||||
|
||||
#define CLK_TABLE_ROM 0x00046E68
|
||||
#define XTAL_TABLE_ROM 0x000046E10
|
||||
|
||||
/* REG_SYS_CLK_CTRL1 */
|
||||
#define BIT_PESOC_EXT32K_CK_SEL (0x00000001 << 8)
|
||||
#define BIT_PESOC_OCP_CPU_CK_SEL (0x00000007 << 4)
|
||||
#define BIT_PESOC_EELDR_CK_SEL (0x00000001 << 0)
|
||||
|
||||
/* REG_SYS_SYSPLL_CTRL1 */
|
||||
/* 1:200MHz, 0:166.666MHz */
|
||||
#define BIT_SYS_SYSPLL_CL200M_SEL (0x00000001 << 17)
|
||||
/* 1:external source 0:PLL */
|
||||
#define BIT_SYS_SYSPLL_CK500K_SEL (0x00000001 << 15)
|
||||
/* enable CK200M */
|
||||
#define BIT_SYS_SYSPLL_CK200M_EN (0x00000001 << 14)
|
||||
/* 1: enable CK_SDRAM */
|
||||
#define BIT_SYS_SYSPLL_CKSDR_EN (0x00000001 << 13)
|
||||
/* SDR PLL select: 00/01/10/11 no clock/25M/50M/100M */
|
||||
#define BIT_SYS_SYSPLL_CKSDR_DIV (0x00000003 << 11)
|
||||
/* 1:enable CK24.576M PLL */
|
||||
#define BIT_SYS_SYSPLL_CK24P576_EN (0x00000001 << 10)
|
||||
/* 1: enable CK22.5792M PLL */
|
||||
#define BIT_SYS_SYSPLL_CK22P5792_EN (0x00000001 << 9)
|
||||
/* 1: enable CK83.33M PLL */
|
||||
#define BIT_SYS_SYSPLL_CK83P33M_EN (0x00000001 << 8)
|
||||
/* reg_ps_en Enable phase shift */
|
||||
#define BIT_SYS_SYSPLL_CK_PS_EN (0x00000001 << 7)
|
||||
/* "decide clock phase when reg_ps_enb = 1000/001<30><31>/111: phase 0, 45<34><35>315 */
|
||||
#define BIT_SYS_SYSPLL_CK_PS_SEL (0x00000007 << 4)
|
||||
|
||||
/* REG_SYS_EFUSE_SYSCFG2 */
|
||||
#define BIT_MASK_SYS_EERROM_ANAPAR_SPLL_24_15 (0x000003ff << 21)
|
||||
#define BIT_MASK_SYS_EEROM_ANAPAR_SPLL_05_02 (0x0000000f << 16)
|
||||
#define BIT_MASK_SYS_EEROM_XTAL_STEL_SEL (0x00000003 << 12)
|
||||
#define BIT_MASK_SYS_EEROM_XTAL_FREQ_SEL (0x0000000f << 8)
|
||||
|
||||
void dump_hex(const void *data, size_t size, const char *prefix) {
|
||||
const uint8_t *bytes = (const uint8_t *)data;
|
||||
for (size_t i = 0; i < size; i++) {
|
||||
if (i % 16 == 0) printf("\n%s%04zX: ", prefix, i);
|
||||
printf("%02X ", bytes[i]);
|
||||
}
|
||||
printf("\n");
|
||||
}
|
||||
|
||||
void analyze_clock_config(void) {
|
||||
printf("\n=== CLOCK CONFIGURATION ===\n");
|
||||
|
||||
// all releveant regs
|
||||
printf("\nRegister Values (Raw):\n");
|
||||
printf("CLK_CTRL1: 0x%08X\n", SYSTEM_CTRL->CLK_CTRL1);
|
||||
printf("SYSPLL_CTRL1: 0x%08X\n", SYSTEM_CTRL->SYSPLL_CTRL1);
|
||||
printf("EFUSE_SYSCFG2: 0x%08X\n", SYSTEM_CTRL->EFUSE_SYSCFG[2]);
|
||||
|
||||
// CLK_CTRL1
|
||||
uint32_t clk_ctrl1 = SYSTEM_CTRL->CLK_CTRL1;
|
||||
printf("\nCLK_CTRL1:\n");
|
||||
printf(" EXT32K_CK_SEL: %d\n",
|
||||
(clk_ctrl1 & BIT_PESOC_EXT32K_CK_SEL) ? 1 : 0);
|
||||
printf(" OCP_CPU_CK_SEL: %d\n",
|
||||
(clk_ctrl1 & BIT_PESOC_OCP_CPU_CK_SEL) >> 4);
|
||||
printf(" EELDR_CK_SEL: %d\n",
|
||||
(clk_ctrl1 & BIT_PESOC_EELDR_CK_SEL) ? 1 : 0);
|
||||
|
||||
// SYSPLL_CTRL1
|
||||
uint32_t syspll_ctrl1 = SYSTEM_CTRL->SYSPLL_CTRL1;
|
||||
printf("\nSYSPLL_CTRL1:\n");
|
||||
printf(" CL200M_SEL: %d\n",
|
||||
(syspll_ctrl1 & BIT_SYS_SYSPLL_CL200M_SEL) ? 1 : 0);
|
||||
printf(" CK500K_SEL: %d\n",
|
||||
(syspll_ctrl1 & BIT_SYS_SYSPLL_CK500K_SEL) ? 1 : 0);
|
||||
printf(" CK200M_EN: %d\n",
|
||||
(syspll_ctrl1 & BIT_SYS_SYSPLL_CK200M_EN) ? 1 : 0);
|
||||
printf(" CKSDR_EN: %d\n",
|
||||
(syspll_ctrl1 & BIT_SYS_SYSPLL_CKSDR_EN) ? 1 : 0);
|
||||
printf(" CKSDR_DIV: %d\n",
|
||||
(syspll_ctrl1 & BIT_SYS_SYSPLL_CKSDR_DIV) >> 11);
|
||||
printf(" CK24P576_EN: %d\n",
|
||||
(syspll_ctrl1 & BIT_SYS_SYSPLL_CK24P576_EN) ? 1 : 0);
|
||||
printf(" CK22P5792_EN: %d\n",
|
||||
(syspll_ctrl1 & BIT_SYS_SYSPLL_CK22P5792_EN) ? 1 : 0);
|
||||
printf(" CK83P33M_EN: %d\n",
|
||||
(syspll_ctrl1 & BIT_SYS_SYSPLL_CK83P33M_EN) ? 1 : 0);
|
||||
printf(" CK_PS_EN: %d\n",
|
||||
(syspll_ctrl1 & BIT_SYS_SYSPLL_CK_PS_EN) ? 1 : 0);
|
||||
printf(" CK_PS_SEL: %d\n",
|
||||
(syspll_ctrl1 & BIT_SYS_SYSPLL_CK_PS_SEL) >> 4);
|
||||
|
||||
// EFUSE_SYSCFG2
|
||||
uint32_t efuse_syscfg2 = SYSTEM_CTRL->EFUSE_SYSCFG[2];
|
||||
uint32_t spll_24_15 =
|
||||
(efuse_syscfg2 & BIT_MASK_SYS_EERROM_ANAPAR_SPLL_24_15) >> 21;
|
||||
uint32_t spll_05_02 =
|
||||
(efuse_syscfg2 & BIT_MASK_SYS_EEROM_ANAPAR_SPLL_05_02) >> 16;
|
||||
uint32_t xtal_stel_sel =
|
||||
(efuse_syscfg2 & BIT_MASK_SYS_EEROM_XTAL_STEL_SEL) >> 12;
|
||||
uint32_t xtal_freq_sel =
|
||||
(efuse_syscfg2 & BIT_MASK_SYS_EEROM_XTAL_FREQ_SEL) >> 8;
|
||||
|
||||
printf("\nEFUSE_SYSCFG2:\n");
|
||||
printf(" SPLL 24:15 Config: 0x%03X\n", spll_24_15);
|
||||
printf(" SPLL 05:02 Config: 0x%X\n", spll_05_02);
|
||||
printf(" XTAL_STEL_SEL: 0x%X\n", xtal_stel_sel);
|
||||
printf(" XTAL_FREQ_SEL: 0x%X\n", xtal_freq_sel);
|
||||
|
||||
// rom XTAL table
|
||||
printf("\nXTAL Table Contents (first 16 entries):\n");
|
||||
const uint32_t *xtal_table = (const uint32_t *)XTAL_TABLE_ROM;
|
||||
for (int i = 0; i < 16; i++) {
|
||||
printf(" [%d]: %d (0x%x Hz)\n", i, xtal_table[i], xtal_table[i]);
|
||||
}
|
||||
|
||||
// xtal freq
|
||||
uint32_t xtal_freq = xtal_table[xtal_freq_sel];
|
||||
printf("\nSelected Crystal:\n");
|
||||
printf(" Index: %d\n", xtal_freq_sel);
|
||||
printf(" Frequency: %d Hz (0x%08X)\n", xtal_freq, xtal_freq);
|
||||
|
||||
// dump clock table
|
||||
printf("\nClock Table Contents (first 16 entries):\n");
|
||||
const uint8_t *clk_table = (uint8_t *)CLK_TABLE_ROM;
|
||||
for (int i = 0; i < 16; i++) {
|
||||
printf(" [%2d]: %d MHz (0x%x)\n", i, clk_table[i], clk_table[i]);
|
||||
}
|
||||
|
||||
// PLL freq
|
||||
uint32_t pll_base_freq =
|
||||
(syspll_ctrl1 & BIT_SYS_SYSPLL_CL200M_SEL) ? 200000000 : 166666666;
|
||||
printf("\nPLL Frequencies:\n");
|
||||
printf(" Base: %d Hz (0x%x)\n", pll_base_freq, pll_base_freq);
|
||||
printf(
|
||||
" SDR Clock: %d Hz (if enabled)\n",
|
||||
pll_base_freq >> (2 - ((syspll_ctrl1 & BIT_SYS_SYSPLL_CKSDR_DIV) >> 11)));
|
||||
printf(" 83.33M: %d Hz (if enabled)\n", 83330000);
|
||||
printf(" 24.576M: %d Hz (if enabled)\n", 24576000);
|
||||
printf(" 22.5792M: %d Hz (if enabled)\n", 22579200);
|
||||
|
||||
// some rom table
|
||||
uint32_t cpu_clock_sel = (clk_ctrl1 & BIT_PESOC_OCP_CPU_CK_SEL) >> 4;
|
||||
uint32_t cpu_freq = clk_table[cpu_clock_sel];
|
||||
printf("\nCPU Configuration:\n");
|
||||
printf(" Clock Selection Index: %d\n", cpu_clock_sel);
|
||||
printf(" Frequency: %d MHz (0x%x)\n", cpu_freq, cpu_freq);
|
||||
|
||||
uint32_t xtal_to_pll = (pll_base_freq / (xtal_freq / 1000));
|
||||
uint32_t pll_to_cpu =
|
||||
((uint32_t)(cpu_freq * 1000000UL) / (pll_base_freq / 1000));
|
||||
uint32_t xtal_to_cpu =
|
||||
((uint32_t)(cpu_freq * 1000000UL) / (xtal_freq / 1000));
|
||||
|
||||
printf("\nFrequency Relationships (x1000):\n");
|
||||
printf(" XTAL to PLL Base: %x.%03x\n", xtal_to_pll / 1000,
|
||||
xtal_to_pll % 1000);
|
||||
printf(" PLL Base to CPU: %x.%03x\n", pll_to_cpu / 1000, pll_to_cpu % 1000);
|
||||
printf(" XTAL to CPU: %x.%03x\n", xtal_to_cpu / 1000,
|
||||
xtal_to_cpu % 1000);
|
||||
}
|
||||
|
||||
int main(void) {
|
||||
printf("hello from main\n");
|
||||
printf("[main]\n");
|
||||
|
||||
PERI_ON->SOC_PERI_FUNC1_EN |= BIT_PERI_GPIO_EN;
|
||||
PERI_ON->PESOC_CLK_CTRL |= APBPeriph_GPIO_CLOCK;
|
||||
PINMUX_Config(_PA_0, PINMUX_FN_GPIO);
|
||||
PINMUX_ConfigPadPull(_PA_0, GPIO_PuPd_DOWN);
|
||||
GPIOA->DDR |= (1 << 0);
|
||||
uint32_t primask = __get_PRIMASK();
|
||||
__disable_irq();
|
||||
|
||||
SYSTEM_CTRL->CLK_CTRL1 = (SYSTEM_CTRL->CLK_CTRL1 & ~0x70) | (2 << 4);
|
||||
|
||||
if (!primask) {
|
||||
__enable_irq();
|
||||
}
|
||||
|
||||
analyze_clock_config();
|
||||
|
||||
// __asm volatile("udf #0");
|
||||
// DelayMs(5000);
|
||||
// NVIC_SystemReset();
|
||||
|
||||
// print_wifi_version();
|
||||
// wifi_init();
|
||||
// delay_ms(3000);
|
||||
|
||||
// PERI_ON->SOC_PERI_FUNC1_EN |= BIT_PERI_GPIO_EN;
|
||||
// PERI_ON->PESOC_CLK_CTRL |= APBPeriph_GPIO_CLOCK;
|
||||
// PINMUX_Config(_PA_0, PINMUX_FN_GPIO);
|
||||
// PINMUX_ConfigPadPull(_PA_0, GPIO_PuPd_DOWN);
|
||||
// GPIOA->DDR |= (1 << 0);
|
||||
// uint32_t c = 0;
|
||||
|
||||
while (1) {
|
||||
GPIOA->DR |= (1 << 0);
|
||||
delay_ms(2000);
|
||||
GPIOA->DR &= ~(1 << 0);
|
||||
delay_ms(2000);
|
||||
// GPIOA->DR |= (1 << 0);
|
||||
// delay_ms(1000);
|
||||
// GPIOA->DR &= ~(1 << 0);
|
||||
// delay_ms(1000);
|
||||
}
|
||||
}
|
||||
|
||||
Reference in New Issue
Block a user