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chore: refactor pinmux

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Mira
2024-12-09 02:36:47 +06:00
parent a2ce0a42f5
commit 44faaec560
2 changed files with 20 additions and 23 deletions
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35
include/rtl8710bx.h
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@@ -386,7 +386,7 @@ typedef struct {
__IO uint32_t OSC32K_REG_CTRL0; /* 0x0274 */ __IO uint32_t OSC32K_REG_CTRL0; /* 0x0274 */
__IO uint32_t OSC32K_REG_CTRL1; /* 0x0278 */ __IO uint32_t OSC32K_REG_CTRL1; /* 0x0278 */
__IO uint32_t THERMAL_METER_CTRL; /* 0x027C */ __IO uint32_t THERMAL_METER_CTRL; /* 0x027C */
__IO uint32_t GPIO_PINMUX_CTRL[24]; /* 0x0280-0x02DC */ __IO uint32_t GPIO_PINMUX_CTRL[24]; /* 0x0280-0x02DC: Pin Multiplexing */
__IO uint32_t PON_PINMUX_CTRL; /* 0x02E0 */ __IO uint32_t PON_PINMUX_CTRL; /* 0x02E0 */
uint32_t RESERVED5[6]; /* 0x02E4-0x02F8 */ uint32_t RESERVED5[6]; /* 0x02E4-0x02F8 */
__IO uint32_t FW_PPROTECT_KEY_CTRL; /* 0x02FC */ __IO uint32_t FW_PPROTECT_KEY_CTRL; /* 0x02FC */
@@ -394,11 +394,6 @@ typedef struct {
__IO uint32_t PESOC_SOC_CTRL; /* 0x0304 */ __IO uint32_t PESOC_SOC_CTRL; /* 0x0304 */
} PERI_ON_TypeDef; } PERI_ON_TypeDef;
/* Pin Multiplexing */
typedef struct {
__IO uint32_t PADCTR[21]; /*Pad control register */
} PINMUX_TypeDef;
/* /*
* AMEBAZ_TIMER Register Declaration * AMEBAZ_TIMER Register Declaration
* TIM1 have 6 CCR registers: bit[15:0] is CCR, bit[31:24] is CCMR * TIM1 have 6 CCR registers: bit[15:0] is CCR, bit[31:24] is CCMR
@@ -1129,7 +1124,6 @@ typedef struct {
#define NCO1_REG_BASE 0x40000080 #define NCO1_REG_BASE 0x40000080
#define BACKUP_REG_BASE 0x40000138 #define BACKUP_REG_BASE 0x40000138
#define NCO2_REG_BASE 0x4000026C #define NCO2_REG_BASE 0x4000026C
#define PINMUX_REG_BASE 0x40000280
#define GPIO_REG_BASE 0x40001000 #define GPIO_REG_BASE 0x40001000
#define TIMER_REG_BASE 0x40002000 #define TIMER_REG_BASE 0x40002000
@@ -1171,7 +1165,6 @@ typedef struct {
#define SYSTEM_CTRL ((SYSTEM_CTRL_TypeDef *)SYSTEM_CTRL_BASE) #define SYSTEM_CTRL ((SYSTEM_CTRL_TypeDef *)SYSTEM_CTRL_BASE)
#define PERI_ON ((PERI_ON_TypeDef *)PERI_ON_BASE) #define PERI_ON ((PERI_ON_TypeDef *)PERI_ON_BASE)
#define PINMUX ((PINMUX_TypeDef *)PINMUX_REG_BASE)
#define GPIO ((GPIO_TypeDef *)(GPIO_REG_BASE)) #define GPIO ((GPIO_TypeDef *)(GPIO_REG_BASE))
#define GPIOA ((GPIO_Port_TypeDef *)(GPIO_REG_BASE + 0x00)) #define GPIOA ((GPIO_Port_TypeDef *)(GPIO_REG_BASE + 0x00))
@@ -1633,21 +1626,27 @@ typedef struct {
#define PAD_DRV_STRENGTH_6 (0x00000006 << 9) #define PAD_DRV_STRENGTH_6 (0x00000006 << 9)
#define PAD_DRV_STRENGTH_7 (0x00000007 << 9) #define PAD_DRV_STRENGTH_7 (0x00000007 << 9)
static inline void PINMUX_Config(uint32_t pin, uint32_t func) { #define PINMUX_GET_REG_SHIFT(pin, reg, shift) \
volatile uint32_t *reg = &PERI_ON->GPIO_PINMUX_CTRL[pin >> 1]; volatile uint32_t *reg = &PERI_ON->GPIO_PINMUX_CTRL[pin >> 1]; \
uint32_t shift = (pin & 1) << 4; uint32_t shift = (pin & 1) << 4
uint32_t mask = 0xFFFF << shift;
*reg = (*reg & ~mask) | (func << shift); static inline void PINMUX_ConfigMasked(uint32_t pin, uint32_t value,
uint32_t mask) {
PINMUX_GET_REG_SHIFT(pin, reg, shift);
*reg = (*reg & ~(mask << shift)) | (value << shift);
}
static inline void PINMUX_ConfigFn(uint32_t pin, uint32_t func) {
PINMUX_ConfigMasked(pin, func, 0xFFFF);
} }
static inline void PINMUX_ConfigPadPull(uint8_t pin, uint8_t pull_type) { static inline void PINMUX_ConfigPadPull(uint8_t pin, uint8_t pull_type) {
uint32_t reg_index = pin >> 1; PINMUX_ConfigMasked(pin, pull_type, 0xC0U);
uint32_t bit_pos = (pin & 1) << 4; }
uint32_t mask = 0xC0U << bit_pos;
volatile uint32_t *pad_ctrl = &PINMUX->PADCTR[reg_index];
*pad_ctrl = (*pad_ctrl & ~mask) | (pull_type << bit_pos); static inline void PINMUX_Config(uint32_t pin, uint32_t func,
uint8_t pull_type) {
PINMUX_ConfigMasked(pin, func | ((uint32_t)pull_type << 6), 0xFFFF);
} }
/* rtl8711b_gpio.h */ /* rtl8711b_gpio.h */

6
src/main.c
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@@ -18,10 +18,8 @@ int main(void) {
PERI_ON->SOC_PERI_FUNC1_EN |= BIT_PERI_GPIO_EN; PERI_ON->SOC_PERI_FUNC1_EN |= BIT_PERI_GPIO_EN;
PERI_ON->PESOC_CLK_CTRL |= APBPeriph_GPIO_CLOCK; PERI_ON->PESOC_CLK_CTRL |= APBPeriph_GPIO_CLOCK;
PINMUX_Config(_PA_0, PINMUX_FN_GPIO); PINMUX_Config(_PA_0, PINMUX_FN_GPIO, GPIO_PuPd_DOWN);
PINMUX_Config(_PA_23, PINMUX_FN_GPIO); PINMUX_Config(_PA_23, PINMUX_FN_GPIO, GPIO_PuPd_NOPULL);
PINMUX_ConfigPadPull(_PA_0, GPIO_PuPd_DOWN);
PINMUX_ConfigPadPull(_PA_23, GPIO_PuPd_NOPULL);
GPIOA->DDR |= (1 << 0) | (1 << 23); GPIOA->DDR |= (1 << 0) | (1 << 23);
// GPIOA->DDR |= (1 << 23); // GPIOA->DDR |= (1 << 23);