mira/rtl8710bx-re
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

chore: wifi??git add .?

Browse Source
This commit is contained in:
Mira
2024-12-07 17:15:25 +06:00
parent 57e6815a2f
commit 535abe4b13
3 changed files with 588 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

413
include/rtl8710bx.h
View File

@@ -681,6 +681,418 @@ typedef struct {
__IO uint32_t QOS_CTRL; /* QoS control */
} USOC_REG_TypeDef;
/* 0x0000h ~ 0x00FFh System Configuration */
typedef struct {
__IO uint16_t ISO_CTRL; // 0x0000, 2 Byte
__IO uint16_t FUNC_EN; // 0x0002, 2 Byte
__IO uint32_t APS_FSMCO; // 0x0004, 4 Byte
__IO uint16_t CLKR; // 0x0008, 2 Byte
__IO uint16_t CR_9346; // 0x000A, 2 Byte
__IO uint16_t EE_VPD; // 0x000C, 2 Byte
__IO uint8_t AFE_MISC; // 0x0010, 1 Byte
__IO uint8_t SPS0_CTRL[7]; // 0x0011, 7 Byte
__IO uint32_t SPS_OCP_CFG; // 0x0018, 4 Byte
__IO uint8_t RSV_CTRL[3]; // 0x001C, 3 Byte
__IO uint8_t RF_CTRL; // 0x001F, 1 Byte
__IO uint8_t LPLDO_CTRL; // 0x0023, 1 Byte
__IO uint32_t AFE_XTAL_CTRL; // 0x0024, 4 Byte
__IO uint32_t AFE_PLL_CTRL; // 0x0028, 4 Byte
__IO uint32_t MAC_PLL_CTRL_EXT; // 0x002C, 4 Byte
__IO uint32_t EFUSE_CTRL; // 0x0030
__IO uint32_t EFUSE_TEST; // 0x0034
__IO uint32_t PWR_DATA; // 0x0038
__IO uint32_t CAL_TIMER; // 0x003C
__I uint16_t ACLK_MON; // 0x003E, Read-only
__IO uint16_t GPIO_MUXCFG; // 0x0040
__IO uint16_t GPIO_IO_SEL; // 0x0042
__IO uint8_t MAC_PINMUX_CFG; // 0x0043
__IO uint32_t GPIO_PIN_CTRL; // 0x0044
__IO uint32_t GPIO_INTM; // 0x0048
__IO uint8_t LEDCFG0; // 0x004C
__IO uint8_t LEDCFG1; // 0x004D
__IO uint8_t LEDCFG2; // 0x004E
__IO uint8_t LEDCFG3; // 0x004F
__IO uint32_t FSIMR; // 0x0050
__I uint32_t FSISR; // 0x0054, Status register
__IO uint32_t HSIMR; // 0x0058
__I uint32_t HSISR; // 0x005C, Status register
__IO uint32_t GPIO_EXT_CTRL; // 0x0060
__IO uint32_t MULTI_FUNC_CTRL; // 0x0068
__I uint32_t GPIO_STATUS; // 0x006C, Status register
__IO uint32_t SDIO_CTRL; // 0x0070
__IO uint32_t OPT_CTRL; // 0x0074
__IO uint32_t AFE_XTAL_CTRL_EXT; // 0x0078
__IO uint32_t MCUFWDL; // 0x0090
__I uint32_t BT_PATCH_STATUS; // 0x0088, Status register
__IO uint32_t HIMR0; // 0x00B0
__I uint32_t HISR0; // 0x00B4, Status register
__IO uint32_t HIMR1; // 0x00B8
__I uint32_t HISR1; // 0x00BC, Status register
__IO uint32_t PMC_DBG_CTRL2; // 0x00CC
__IO uint8_t EFUSE_BURN_GNT; // 0x00CF
__I uint32_t HPON_FSM; // 0x00EC, FSM state
__IO uint32_t SYS_CFG; // 0x00F0
__IO uint32_t SYS_CFG1; // 0x00FC
__I uint8_t ROM_VERSION; // 0x00FD, Read-only version
} WiFi_SYS_TypeDef;
/* 0x0100h ~ 0x01FFh MACTOP General Configuration */
typedef struct {
__IO uint32_t CR; /* 0x0100 Control Register */
__IO uint32_t PBP; /* 0x0104 Packet Buffer Parameter */
__IO uint16_t PKT_BUFF_ACCESS_CTRL; /* 0x0106 Packet Buffer Access Control */
uint16_t RESERVED0; /* 0x0108-0x0109 */
__IO uint32_t TRXDMA_CTRL; /* 0x010C TRX DMA Control */
uint8_t RESERVED1[4]; /* 0x0110-0x0113 */
__IO uint32_t TRXFF_BNDY; /* 0x0114 TRX FIFO Boundary */
__I uint32_t TRXFF_STATUS; /* 0x0118 TRX FIFO Status */
__I uint32_t RXFF_PTR; /* 0x011C RX FIFO Pointer */
uint8_t RESERVED2[0x12]; /* 0x0120-0x012E */
__IO uint8_t CPWM; /* 0x012F Control Power Management */
uint8_t RESERVED3[8]; /* 0x0130-0x0137 */
__IO uint32_t FTIMR; /* 0x0138 FW Timer Interrupt Mask Register */
uint8_t RESERVED4[4]; /* 0x013C-0x013F */
__IO uint16_t PKTBUF_DBG_CTRL; /* 0x0140 Packet Buffer Debug Control */
__IO uint16_t RXPKTBUF_CTRL; /* 0x0142 RX Packet Buffer Control */
__I uint32_t PKTBUF_DBG_DATA_L; /* 0x0144 Packet Buffer Debug Data Low */
__I uint32_t PKTBUF_DBG_DATA_H; /* 0x0148 Packet Buffer Debug Data High */
__IO uint32_t TC0_CTRL; /* 0x0150 TC0 Control Register */
__IO uint32_t TC1_CTRL; /* 0x0154 TC1 Control Register */
__IO uint32_t TC2_CTRL; /* 0x0158 TC2 Control Register */
__IO uint32_t TC3_CTRL; /* 0x015C TC3 Control Register */
__IO uint32_t TC4_CTRL; /* 0x0160 TC4 Control Register */
__IO uint32_t TCUNIT_BASE; /* 0x0164 TC Unit Base */
__IO uint32_t RSVD3; /* 0x0168 Reserved */
uint8_t RESERVED5[0x34]; /* 0x016C-0x019F */
__I uint8_t C2HEVT_MSG_NORMAL; /* 0x01A0 C2H Event Message Normal */
__I uint8_t C2HEVT_CMD_SEQ; /* 0x01A1 C2H Event Command Sequence */
__I uint8_t
C2HEVT_CMD_CONTENT[12]; /* 0x01A2-0x01AD C2H Event Command Content */
__I uint8_t C2HEVT_CMD_LEN; /* 0x01AE C2H Event Command Length */
__O uint8_t C2HEVT_CLEAR; /* 0x01AF C2H Event Clear */
__IO uint32_t MCUTST_1; /* 0x01C0 MCU Test 1 */
uint8_t RESERVED6[3]; /* 0x01C4-0x01C6 */
__IO uint8_t MCUTST_WOWLAN; /* 0x01C7 MCU Test WOWLAN */
__IO uint32_t FMETHR; /* 0x01C8 FW Message Exchange Threshold */
__IO uint32_t HMETFR; /* 0x01CC Host Message Exchange Threshold */
__IO uint32_t HMEBOX_0; /* 0x01D0 Host Message Box 0 */
__IO uint32_t HMEBOX_1; /* 0x01D4 Host Message Box 1 */
__IO uint32_t HMEBOX_2; /* 0x01D8 Host Message Box 2 */
__IO uint32_t HMEBOX_3; /* 0x01DC Host Message Box 3 */
__IO uint32_t LLT_INIT; /* 0x01E0 LLT Init */
uint8_t RESERVED7[0xC]; /* 0x01E4-0x01EF */
__IO uint32_t HMEBOX_EXT0; /* 0x01F0 Host Message Box Extension 0 */
__IO uint32_t HMEBOX_EXT1; /* 0x01F4 Host Message Box Extension 1 */
__IO uint32_t HMEBOX_EXT2; /* 0x01F8 Host Message Box Extension 2 */
__IO uint32_t HMEBOX_EXT3; /* 0x01FC Host Message Box Extension 3 */
} WiFi_MAC_TypeDef;
/* 0x0200h ~ 0x027Fh TXDMA Configuration */
typedef struct {
__IO uint32_t RQPN; /* 0x0200 Release Queue Page Number */
__IO uint32_t FIFOPAGE; /* 0x0204 FIFO Page */
__IO uint32_t TDECTRL; /* 0x0208 TX DMA Engine Control */
__IO uint32_t TXDMA_OFFSET_CHK; /* 0x020C TX DMA Offset Check */
__I uint32_t TXDMA_STATUS; /* 0x0210 TX DMA Status */
__IO uint32_t RQPN_NPQ; /* 0x0214 Release Queue Page Number NPQ */
uint8_t RESERVED1[0x10]; /* 0x0218-0x0227 */
__IO uint32_t TDECTRL1; /* 0x0228 TX DMA Engine Control 1 */
uint8_t RESERVED2[0x54]; /* 0x022C-0x027F */
} WiFi_TXDMA_TypeDef;
/* 0x0280h ~ 0x02FFh RXDMA Configuration */
typedef struct {
__IO uint32_t RXDMA_AGG_PG_TH; /* 0x0280 RX DMA Aggregation Page Threshold */
__IO uint32_t FW_UPD_RDPTR; /* 0x0284 Firmware Update Read Pointer */
__IO uint16_t RXDMA_CONTROL; /* 0x0286 RX DMA Control */
__I uint8_t RXPKT_NUM; /* 0x0287 RX Packet Number */
__I uint32_t RXDMA_STATUS; /* 0x0288 RX DMA Status */
uint8_t RESERVED1[4]; /* 0x028C-0x028F */
__IO uint32_t RXDMA_PRO; /* 0x0290 RX DMA PRO */
uint8_t RESERVED2[0x28]; /* 0x0294-0x02BB */
__IO uint32_t EARLY_MODE_CONTROL; /* 0x02BC Early Mode Control */
uint8_t RESERVED3[0x30]; /* 0x02C0-0x02EF */
__IO uint32_t RSVD5; /* 0x02F0 Reserved */
__IO uint32_t RSVD6; /* 0x02F4 Reserved */
uint8_t RESERVED4[8]; /* 0x02F8-0x02FF */
} WiFi_RXDMA_TypeDef;
/* 0x0300h ~ 0x03FFh LxBUS hal_com_reg.h */
/**
* TODO: this is VERY LIKELY wrong, lxbus_ops.o
* DMA descriptors aren't arranged sequentially
* spacing between TX descriptors is unusual
* 32K control register (at 0x3D9)???
*/
typedef struct {
/* 0x0300 - Control Register */
volatile uint32_t CTRL; /* 0x0300 - Control register */
volatile uint32_t RESERVED1[1]; /* 0x0304 */
volatile uint32_t TX4_DESC; /* 0x0308 - TX Ring 4 Descriptor */
volatile uint32_t RESERVED2[1]; /* 0x030C */
volatile uint32_t TX5_DESC; /* 0x0310 - TX Ring 5 Descriptor */
volatile uint32_t RESERVED3[1]; /* 0x0314 */
volatile uint32_t TX0_DESC; /* 0x0318 - TX Ring 0 Descriptor */
volatile uint32_t RESERVED4[1]; /* 0x031C */
volatile uint32_t TX1_DESC; /* 0x0320 - TX Ring 1 Descriptor */
volatile uint32_t RESERVED5[1]; /* 0x0324 */
volatile uint32_t TX2_DESC; /* 0x0328 - TX Ring 2 Descriptor */
volatile uint32_t RESERVED6[1]; /* 0x032C */
volatile uint32_t TX3_DESC; /* 0x0330 - TX Ring 3 Descriptor */
volatile uint32_t RESERVED7[1]; /* 0x0334 */
volatile uint32_t RX_DESC; /* 0x0338 - RX Ring Descriptor */
volatile uint32_t RESERVED8[1]; /* 0x033C */
volatile uint32_t TX6_DESC; /* 0x0340 - TX Ring 6 Descriptor */
volatile uint32_t RESERVED9[15]; /* 0x0344-0x037F */
/* DMA Configuration Registers */
volatile uint16_t
DMA_CFG[14]; /* 0x0380-0x039B - DMA Configuration registers */
volatile uint8_t RESERVED10[61]; /* 0x039C-0x03D8 */
/* 32K Control Register */
volatile uint8_t K32_CTRL; /* 0x03D9 - 32K Control register */
volatile uint8_t RESERVED11[14]; /* 0x03DA-0x03E7 */
/* Additional Control Registers */
volatile uint32_t INT_MASK; /* 0x03E8 - Interrupt Mask */
volatile uint32_t INT_STATUS; /* 0x03EC - Interrupt Status */
} WiFi_LXBUS_TypeDef;
/* bits */
#define LXBUS_CTRL_BIT8 (1 << 8) /* Control register bit 8 */
#define LXBUS_K32_CTRL_BIT0 (1 << 0) /* 32K Control bit 0 */
#define LXBUS_K32_CTRL_BIT6 (1 << 6) /* 32K Control bit 6 */
#define LXBUS_K32_CTRL_BIT7 (1 << 7) /* 32K Control bit 7 */
/* DMA config */
#define LXBUS_DMA_CFG_TYPE1 0x1004 /* DMA config type 1 */
#define LXBUS_DMA_CFG_TYPE2 0x2004 /* DMA config type 2 */
#define LXBUS_DMA_CFG_TYPE3 0x1002 /* DMA config type 3 */
/* 0x0400h ~ 0x047Fh Protocol Configuration */
typedef struct {
/* Queue Information Registers */
__IO uint32_t VOQ_INFORMATION; /* 0x0400 VO Queue Information */
__IO uint32_t VIQ_INFORMATION; /* 0x0404 VI Queue Information */
__IO uint32_t BEQ_INFORMATION; /* 0x0408 BE Queue Information */
__IO uint32_t BKQ_INFORMATION; /* 0x040C BK Queue Information */
__IO uint32_t MGQ_INFORMATION; /* 0x0410 MG Queue Information */
__IO uint32_t HGQ_INFORMATION; /* 0x0414 HG Queue Information */
__IO uint32_t BCNQ_INFORMATION; /* 0x0418 BCN Queue Information */
__I uint16_t TXPKT_EMPTY; /* 0x041A TX Packet Empty */
uint8_t RESERVED1[4]; /* 0x041C-0x041F */
/* Control Registers */
__IO uint32_t FWHW_TXQ_CTRL; /* 0x0420 FWHW TX Queue Control */
__IO uint8_t HWSEQ_CTRL; /* 0x0423 HW Sequence Control */
__IO uint8_t TXPKTBUF_BCNQ_BDNY; /* 0x0424 TX Packet Buffer BCNQ Boundary */
__IO uint8_t TXPKTBUF_MGQ_BDNY; /* 0x0425 TX Packet Buffer MGQ Boundary */
__IO uint8_t LIFECTRL_CTRL; /* 0x0426 Life Control */
__IO uint8_t MULTI_BCNQ_OFFSET; /* 0x0427 Multi BCNQ Offset */
__IO uint16_t SPEC_SIFS; /* 0x0428 Specific SIFS */
__IO uint16_t RL; /* 0x042A Retry Limit */
__IO uint32_t TXBF_CTRL; /* 0x042C TX Beamforming Control */
/* Frame Rate Control */
__IO uint64_t
DARFRC; /* 0x0430-0x0437 Data Auto Response Frame Rate Control */
__IO uint64_t
RARFRC; /* 0x0438-0x043F Response Auto Response Frame Rate Control */
__IO uint32_t RRSR; /* 0x0440 Response Rate Set */
__IO uint64_t ARFR0; /* 0x0444-0x044B Auto Response Frame Rate 0 */
__IO uint64_t ARFR1; /* 0x044C-0x0453 Auto Response Frame Rate 1 */
__IO uint16_t CCK_CHECK; /* 0x0454 CCK Check */
__IO uint16_t AMPDU_MAX_TIME; /* 0x0456 AMPDU Max Time */
__IO uint8_t
TXPKTBUF_BCNQ_BDNY1; /* 0x0457 TX Packet Buffer BCNQ Boundary 1 */
/* AMPDU and Buffer Control */
__IO uint32_t AMPDU_MAX_LENGTH; /* 0x0458 AMPDU Max Length */
uint8_t RESERVED2[1]; /* 0x045C */
__IO uint8_t
TXPKTBUF_WMAC_LBK_BF_HD; /* 0x045D TX Packet Buffer WMAC LBK BF HD */
uint8_t RESERVED3[1]; /* 0x045E */
__IO uint8_t NDPA_OPT_CTRL; /* 0x045F NDPA Option Control */
__IO uint32_t FAST_EDCA_CTRL; /* 0x0460 Fast EDCA Control */
__IO uint8_t RD_RESP_PKT_TH; /* 0x0463 RD Response Packet Threshold */
uint8_t RESERVED4[0x1A]; /* 0x0464-0x047D */
__IO uint8_t SPC_W_PTR; /* 0x047E SPC Write Pointer */
__IO uint8_t SPC_R_PTR; /* 0x047F SPC Read Pointer */
uint8_t RESERVED5[3]; /* 0x0480-0x0482 */
__IO uint8_t DATA_SC; /* 0x0483 Data Sequence Control */
uint8_t RESERVED6[0x28]; /* 0x0484-0x04AB */
__IO uint32_t TXRPT_START_OFFSET; /* 0x04AC TX Report Start Offset */
uint8_t RESERVED7[4]; /* 0x04B0-0x04B3 */
__IO uint32_t POWER_STAGE1; /* 0x04B4 Power Stage 1 */
__IO uint32_t POWER_STAGE2; /* 0x04B8 Power Stage 2 */
__IO uint32_t AMPDU_BURST_MODE; /* 0x04BC AMPDU Burst Mode */
__IO uint16_t PKT_VO_VI_LIFE_TIME; /* 0x04C0 Packet VO/VI Life Time */
__IO uint16_t PKT_BE_BK_LIFE_TIME; /* 0x04C2 Packet BE/BK Life Time */
__IO uint32_t STBC_SETTING; /* 0x04C4 STBC Setting */
__IO uint8_t HT_SINGLE_AMPDU; /* 0x04C7 HT Single AMPDU */
__IO uint32_t PROT_MODE_CTRL; /* 0x04C8 Protection Mode Control */
__IO uint16_t MAX_AGGR_NUM; /* 0x04CA Maximum Aggregation Number */
__IO uint8_t RTS_MAX_AGGR_NUM; /* 0x04CB RTS Maximum Aggregation Number */
__IO uint32_t BAR_MODE_CTRL; /* 0x04CC BAR Mode Control */
__IO uint8_t RA_TRY_RATE_AGG_LMT; /* 0x04CF RA Try Rate Aggregation Limit */
__IO uint32_t MACID_PKT_DROP0; /* 0x04D0 MACID Packet Drop 0 */
uint8_t RESERVED[0x2C]; /* 0x04D4-0x04FF */
} WiFi_PROT_TypeDef;
/* 0x0500h ~ 0x05FFh EDCA Configuration */
typedef struct {
__IO uint32_t VO_PARAM; /* 0x0500 EDCA VO parameter */
__IO uint32_t VI_PARAM; /* 0x0504 EDCA VI parameter */
__IO uint32_t BE_PARAM; /* 0x0508 EDCA BE parameter */
__IO uint32_t BK_PARAM; /* 0x050C EDCA BK parameter */
__IO uint32_t BCNTCFG; /* 0x0510 Beacon configuration */
__IO uint16_t PIFS; /* 0x0512 PIFS timing */
__IO uint8_t RDG_PIFS; /* 0x0513 RDG PIFS timing */
__IO uint16_t SIFS_CTX; /* 0x0514 SIFS context timing */
__IO uint16_t SIFS_TRX; /* 0x0516 SIFS TRX timing */
__IO uint16_t AGGR_BREAK_TIME; /* 0x051A Aggregation break time */
__IO uint8_t SLOT; /* 0x051B Slot time */
__IO uint32_t TX_PTCL_CTRL; /* 0x0520 TX protocol control */
__IO uint8_t TXPAUSE; /* 0x0522 TX pause */
__IO uint8_t DIS_TXREQ_CLR; /* 0x0523 Disable TX request clear */
__IO uint32_t RD_CTRL; /* 0x0524 RD control */
uint8_t RESERVED1[24]; /* 0x528-0x540 */
// Format for offset 540h-542h:
// [3:0]: TBTT prohibit setup in unit of 32us. The time for HW getting
// beacon content before TBTT. [7:4]: Reserved. [19:8]: TBTT
// prohibit hold in unit of 32us. The time for HW holding to send the beacon
// packet. [23:20]: Reserved
// Description:
// |
// |<--Setup--|--Hold------------>|
// --------------|----------------------
// |
// TBTT
// Note: We cannot update beacon content to HW or send any AC packets during
// the time between Setup and Hold. Described by Designer Tim and Bruce,
// 2011-01-14.
__IO uint32_t TBTT_PROHIBIT; /* 0x0540 TBTT prohibit */
__IO uint32_t RD_NAV_NXT; /* 0x0544 RD NAV next */
__IO uint16_t NAV_PROT_LEN; /* 0x0546 NAV protection length */
uint8_t RESERVED2[8]; /* 0x548-0x550 */
__IO uint8_t BCN_CTRL; /* 0x0550 Beacon control */
__IO uint8_t BCN_CTRL_1; /* 0x0551 Beacon control 1 */
__IO uint8_t MBID_NUM; /* 0x0552 MBID number */
__IO uint8_t DUAL_TSF_RST; /* 0x0553 Dual TSF reset */
__IO uint16_t BCN_INTERVAL; /* 0x0554 Beacon interval */
uint8_t RESERVED3[2]; /* 0x556-0x558 */
__IO uint8_t DRVERLYINT; /* 0x0558 Driver early interrupt */
__IO uint8_t BCNDMATIM; /* 0x0559 Beacon DMA timing */
__IO uint16_t ATIMWND; /* 0x055A ATIM window */
__IO uint16_t USTIME_TSF; /* 0x055C US time TSF */
__IO uint8_t BCN_MAX_ERR; /* 0x055D Beacon max error */
__IO uint8_t RXTSF_OFFSET_CCK; /* 0x055E RX TSF offset CCK */
__IO uint8_t RXTSF_OFFSET_OFDM; /* 0x055F RX TSF offset OFDM */
__IO uint32_t TSFTR; /* 0x0560 TSF timer */
uint8_t RESERVED4[14]; /* 0x564-0x572 */
__IO uint8_t CTWND; /* 0x0572 CT window */
__IO uint8_t BCNIVLCUNT; /* 0x0573 Beacon interval count */
uint8_t RESERVED5[3]; /* 0x574-0x577 */
__IO uint8_t SECONDARY_CCA_CTRL; /* 0x0577 Secondary CCA control */
uint8_t RESERVED6[8]; /* 0x578-0x580 */
__IO uint32_t PSTIMER; /* 0x0580 PS timer */
__IO uint32_t TIMER0; /* 0x0584 Timer 0 */
__IO uint32_t TIMER1; /* 0x0588 Timer 1 */
uint8_t RESERVED7[52]; /* 0x58C-0x5C0 */
__IO uint32_t ACMHWCTRL; /* 0x05C0 ACM hardware control */
uint8_t RESERVED8[52]; /* 0x5C4-0x5F8 */
__IO uint32_t SCH_TXCMD; /* 0x05F8 Schedule TX command */
uint8_t RESERVED9[4]; /* 0x5FC-0x600 */
} WiFi_EDCA_TypeDef;
/* 0x0600h ~ 0x07FFh WMAC Configuration */
typedef struct {
/* MAC Configuration (0x0600-0x060F) */
__IO uint32_t MAC_CR; /* 0x0600 MAC Configuration Register */
__IO uint32_t TCR; /* 0x0604 Transmission Configuration Register */
__IO uint32_t RCR; /* 0x0608 Receive Configuration Register */
__IO uint8_t RX_PKT_LIMIT; /* 0x060C RX Packet Limit */
__IO uint8_t RX_DLK_TIME; /* 0x060D RX Deadlock Time */
uint8_t RESERVED1[1]; /* 0x060E */
__IO uint8_t RX_DRVINFO_SZ; /* 0x060F RX Driver Info Size */
/* ID Configuration (0x0610-0x0628) */
__IO uint32_t MACID[2]; /* 0x0610 MAC ID */
__IO uint32_t BSSID[2]; /* 0x0618 BSSID */
__IO uint32_t MAR[2]; /* 0x0620 Multicast Address */
__IO uint32_t MBIDCAMCFG; /* 0x0628 MBSSID CAM Configuration */
uint8_t RESERVED2[12]; /* 0x062C-0x0637 */
/* Timing Configuration (0x0638-0x0642) */
__IO uint16_t USTIME_EDCA; /* 0x0638 US Time EDCA */
__IO uint16_t MAC_SPEC_SIFS; /* 0x063A MAC Specific SIFS */
__IO uint16_t RESP_SIFP_CCK; /* 0x063C Response SIFS CCK */
__IO uint16_t RESP_SIFS_OFDM; /* 0x063E Response SIFS OFDM */
__IO uint8_t ACKTO; /* 0x0640 ACK Timeout */
__IO uint8_t CTS2TO; /* 0x0641 CTS2 Timeout */
__IO uint16_t EIFS; /* 0x0642 Extended InterFrame Space */
uint8_t RESERVED3[13]; /* 0x0644-0x0650 */
/* Protocol Control (0x0652-0x0668) */
__IO uint16_t NAV_UPPER; /* 0x0652 NAV Upper (unit of 128) */
uint8_t RESERVED4[14]; /* 0x0654-0x0661 */
__IO uint16_t RTR; /* 0x0662 Response Time Report */
uint8_t RESERVED5[4]; /* 0x0664-0x0667 */
__IO uint32_t TRXPTCL_CTL; /* 0x0668 TRX Protocol Control */
uint8_t RESERVED6[4]; /* 0x066C-0x066F */
/* Security (0x0670-0x0680) */
__IO uint32_t CAMCMD; /* 0x0670 CAM Command */
__IO uint32_t CAMWRITE; /* 0x0674 CAM Write */
__IO uint32_t CAMREAD; /* 0x0678 CAM Read */
__IO uint32_t CAMDBG; /* 0x067C CAM Debug */
__IO uint32_t SECCFG; /* 0x0680 Security Configuration */
uint8_t RESERVED7[12]; /* 0x0684-0x068F */
/* Power Management (0x0690-0x06A8) */
__IO uint16_t WOW_CTRL; /* 0x0690 WoW Control */
__IO uint8_t PS_RX_INFO; /* 0x0692 Power Save RX Info */
__IO uint8_t UAPSD_TID; /* 0x0693 UAPSD TID */
uint8_t RESERVED8[4]; /* 0x0694-0x0697 */
__IO uint32_t WKFMCAM_CMD; /* 0x0698 Wake FM CAM Command */
__IO uint32_t WKFMCAM_RWD; /* 0x069C Wake FM CAM Read/Write Data */
__IO uint16_t RXFLTMAP0; /* 0x06A0 RX Filter Map 0 */
__IO uint16_t RXFLTMAP1; /* 0x06A2 RX Filter Map 1 */
__IO uint16_t RXFLTMAP2; /* 0x06A4 RX Filter Map 2 */
uint8_t RESERVED9[2]; /* 0x06A6-0x06A7 */
__IO uint32_t BCN_PSR_RPT; /* 0x06A8 Beacon Parser Report */
uint8_t RESERVED10[20]; /* 0x06AC-0x06BF */
/* Coexistence & Beamforming (0x06C0-0x06FC) */
__IO uint32_t BT_COEX_TABLE[9]; /* 0x06C0 BT Coexistence Table */
__IO uint32_t BFMER0_INFO[2]; /* 0x06E4 Beamformer 0 Information */
__IO uint32_t BFMER1_INFO[2]; /* 0x06EC Beamformer 1 Information */
__IO uint32_t CSI_RPT_PARAM_BW20; /* 0x06F4 CSI Report Parameter BW20 */
__IO uint32_t CSI_RPT_PARAM_BW40; /* 0x06F8 CSI Report Parameter BW40 */
__IO uint32_t CSI_RPT_PARAM_BW80; /* 0x06FC CSI Report Parameter BW80 */
/* Hardware Port 2 (0x0700-0x0718) */
__IO uint32_t MACID1[2]; /* 0x0700 MAC ID 1 */
__IO uint32_t BSSID1[2]; /* 0x0708 BSSID 1 */
uint8_t RESERVED11[4]; /* 0x0710-0x0713 */
__IO uint32_t BFMEE_SEL; /* 0x0714 Beamformee Selection */
__IO uint32_t SND_PTCL_CTRL; /* 0x0718 Sound Protocol Control */
} WiFi_WMAC_TypeDef;
typedef struct {
WiFi_SYS_TypeDef SYS; /* 0x0000-0x00FF */
WiFi_MAC_TypeDef MAC; /* 0x0100-0x01FF */
WiFi_TXDMA_TypeDef TXDMA; /* 0x0200-0x027F */
WiFi_RXDMA_TypeDef RXDMA; /* 0x0280-0x02FF */
WiFi_LXBUS_TypeDef LXBUS; /* 0x0300-0x03FF */
WiFi_PROT_TypeDef PROT; /* 0x0400-0x047F */
WiFi_EDCA_TypeDef EDCA; /* 0x0500-0x05FF */
WiFi_WMAC_TypeDef WMAC; /* 0x0600-0x07FF */
} WiFi_TypeDef;
/* Peripheral memory map */
#define SPI_FLASH_BASE 0x08000000
@@ -759,6 +1171,7 @@ typedef struct {
#define NCO8M ((NCO8M_TypeDef *)NCO2_REG_BASE)
#define BACKUP_REG ((BACKUP_REG_TypeDef *)BACKUP_REG_BASE)
#define SPIC_CACHE ((SPIC_CACHE_TypeDef *)SPIC_CACHE_BASE)
#define WIFI ((WiFi_TypeDef *)WIFI_REG_BASE)
#define GPIOA ((GPIO_Port_TypeDef *)(GPIO_REG_BASE + 0x00))
#define GPIOB ((GPIO_Port_TypeDef *)(GPIO_REG_BASE + 0x0C))