chore: blinky

include/cmsis/cmsis_compiler.h

@@ -0,0 +1,284 @@
+/*
+ * Copyright (c) 2009-2023 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/*
+ * CMSIS Compiler Generic Header File
+ */
+
+#ifndef __CMSIS_COMPILER_H
+#define __CMSIS_COMPILER_H
+
+#include <stdint.h>
+
+/*
+ * Arm Compiler above 6.10.1 (armclang)
+ */
+#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100)
+  #include "cmsis_armclang.h"
+
+/*
+ * TI Arm Clang Compiler (tiarmclang)
+ */
+#elif defined (__ti__)
+  #include "cmsis_tiarmclang.h"
+
+
+/*
+ * LLVM/Clang Compiler
+ */
+#elif defined ( __clang__ )
+  #include "cmsis_clang.h"
+
+
+/*
+ * GNU Compiler
+ */
+#elif defined ( __GNUC__ )
+  #include "cmsis_gcc.h"
+
+
+/*
+ * IAR Compiler
+ */
+#elif defined ( __ICCARM__ )
+  #include "cmsis_iccarm.h"
+
+
+/*
+ * TI Arm Compiler (armcl)
+ */
+#elif defined ( __TI_ARM__ )
+  #include <cmsis_ccs.h>
+
+  #ifndef   __ASM
+    #define __ASM                                  __asm
+  #endif
+  #ifndef   __INLINE
+    #define __INLINE                               inline
+  #endif
+  #ifndef   __STATIC_INLINE
+    #define __STATIC_INLINE                        static inline
+  #endif
+  #ifndef   __STATIC_FORCEINLINE
+    #define __STATIC_FORCEINLINE                   __STATIC_INLINE
+  #endif
+  #ifndef   __NO_RETURN
+    #define __NO_RETURN                            __attribute__((noreturn))
+  #endif
+  #ifndef   __USED
+    #define __USED                                 __attribute__((used))
+  #endif
+  #ifndef   __WEAK
+    #define __WEAK                                 __attribute__((weak))
+  #endif
+  #ifndef   __PACKED
+    #define __PACKED                               __attribute__((packed))
+  #endif
+  #ifndef   __PACKED_STRUCT
+    #define __PACKED_STRUCT                        struct __attribute__((packed))
+  #endif
+  #ifndef   __PACKED_UNION
+    #define __PACKED_UNION                         union __attribute__((packed))
+  #endif
+  #ifndef   __UNALIGNED_UINT16_WRITE
+    __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+    #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT16_READ
+    __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+    #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT32_WRITE
+    __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+    #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT32_READ
+    __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+    #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __ALIGNED
+    #define __ALIGNED(x)                           __attribute__((aligned(x)))
+  #endif
+  #ifndef   __RESTRICT
+    #define __RESTRICT                             __restrict
+  #endif
+  #ifndef   __COMPILER_BARRIER
+    #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
+    #define __COMPILER_BARRIER()                   (void)0
+  #endif
+  #ifndef __NO_INIT
+    #define __NO_INIT                              __attribute__ ((section (".noinit")))
+  #endif
+  #ifndef __ALIAS
+    #define __ALIAS(x)                             __attribute__ ((alias(x)))
+  #endif
+
+/*
+ * TASKING Compiler
+ */
+#elif defined ( __TASKING__ )
+  /*
+   * The CMSIS functions have been implemented as intrinsics in the compiler.
+   * Please use "carm -?i" to get an up to date list of all intrinsics,
+   * Including the CMSIS ones.
+   */
+
+  #ifndef   __ASM
+    #define __ASM                                  __asm
+  #endif
+  #ifndef   __INLINE
+    #define __INLINE                               inline
+  #endif
+  #ifndef   __STATIC_INLINE
+    #define __STATIC_INLINE                        static inline
+  #endif
+  #ifndef   __STATIC_FORCEINLINE
+    #define __STATIC_FORCEINLINE                   __STATIC_INLINE
+  #endif
+  #ifndef   __NO_RETURN
+    #define __NO_RETURN                            __attribute__((noreturn))
+  #endif
+  #ifndef   __USED
+    #define __USED                                 __attribute__((used))
+  #endif
+  #ifndef   __WEAK
+    #define __WEAK                                 __attribute__((weak))
+  #endif
+  #ifndef   __PACKED
+    #define __PACKED                               __packed__
+  #endif
+  #ifndef   __PACKED_STRUCT
+    #define __PACKED_STRUCT                        struct __packed__
+  #endif
+  #ifndef   __PACKED_UNION
+    #define __PACKED_UNION                         union __packed__
+  #endif
+  #ifndef   __UNALIGNED_UINT16_WRITE
+    __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+    #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT16_READ
+    __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+    #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT32_WRITE
+    __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+    #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT32_READ
+    __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+    #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __ALIGNED
+    #define __ALIGNED(x)                           __align(x)
+  #endif
+  #ifndef   __RESTRICT
+    #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
+    #define __RESTRICT
+  #endif
+  #ifndef   __COMPILER_BARRIER
+    #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
+    #define __COMPILER_BARRIER()                   (void)0
+  #endif
+  #ifndef __NO_INIT
+    #define __NO_INIT                              __attribute__ ((section (".noinit")))
+  #endif
+  #ifndef __ALIAS
+    #define __ALIAS(x)                             __attribute__ ((alias(x)))
+  #endif
+
+/*
+ * COSMIC Compiler
+ */
+#elif defined ( __CSMC__ )
+   #include <cmsis_csm.h>
+
+ #ifndef   __ASM
+    #define __ASM                                  _asm
+  #endif
+  #ifndef   __INLINE
+    #define __INLINE                               inline
+  #endif
+  #ifndef   __STATIC_INLINE
+    #define __STATIC_INLINE                        static inline
+  #endif
+  #ifndef   __STATIC_FORCEINLINE
+    #define __STATIC_FORCEINLINE                   __STATIC_INLINE
+  #endif
+  #ifndef   __NO_RETURN
+    // NO RETURN is automatically detected hence no warning here
+    #define __NO_RETURN
+  #endif
+  #ifndef   __USED
+    #warning No compiler specific solution for __USED. __USED is ignored.
+    #define __USED
+  #endif
+  #ifndef   __WEAK
+    #define __WEAK                                 __weak
+  #endif
+  #ifndef   __PACKED
+    #define __PACKED                               @packed
+  #endif
+  #ifndef   __PACKED_STRUCT
+    #define __PACKED_STRUCT                        @packed struct
+  #endif
+  #ifndef   __PACKED_UNION
+    #define __PACKED_UNION                         @packed union
+  #endif
+  #ifndef   __UNALIGNED_UINT16_WRITE
+    __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+    #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT16_READ
+    __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+    #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT32_WRITE
+    __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+    #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT32_READ
+    __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+    #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __ALIGNED
+    #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
+    #define __ALIGNED(x)
+  #endif
+  #ifndef   __RESTRICT
+    #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
+    #define __RESTRICT
+  #endif
+  #ifndef   __COMPILER_BARRIER
+    #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
+    #define __COMPILER_BARRIER()                   (void)0
+  #endif
+  #ifndef __NO_INIT
+    #define __NO_INIT                              __attribute__ ((section (".noinit")))
+  #endif
+  #ifndef __ALIAS
+    #define __ALIAS(x)                             __attribute__ ((alias(x)))
+  #endif
+
+#else
+  #error Unknown compiler.
+#endif
+
+
+#endif /* __CMSIS_COMPILER_H */
+

include/cmsis/cmsis_version.h

@@ -0,0 +1,44 @@
+/*
+ * Copyright (c) 2009-2023 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/*
+ * CMSIS Core Version Definitions
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CMSIS_VERSION_H
+#define __CMSIS_VERSION_H
+
+/*  CMSIS-Core(M) Version definitions */
+#define __CM_CMSIS_VERSION_MAIN  ( 6U)                                    /*!< \brief [31:16] CMSIS-Core(M) main version */
+#define __CM_CMSIS_VERSION_SUB   ( 1U)                                    /*!< \brief [15:0]  CMSIS-Core(M) sub version */
+#define __CM_CMSIS_VERSION       ((__CM_CMSIS_VERSION_MAIN << 16U) | \
+                                   __CM_CMSIS_VERSION_SUB           )     /*!< \brief CMSIS Core(M) version number */
+
+/*  CMSIS-Core(A) Version definitions */
+#define __CA_CMSIS_VERSION_MAIN  ( 6U)                                    /*!< \brief [31:16] CMSIS-Core(A) main version */
+#define __CA_CMSIS_VERSION_SUB   ( 1U)                                    /*!< \brief [15:0]  CMSIS-Core(A) sub version */
+#define __CA_CMSIS_VERSION       ((__CA_CMSIS_VERSION_MAIN << 16U) | \
+                                   __CA_CMSIS_VERSION_SUB          )      /*!< \brief CMSIS-Core(A) version number */
+
+#endif

include/cmsis/m-profile/armv7m_cachel1.h

@@ -0,0 +1,439 @@
+/*
+ * Copyright (c) 2020-2021 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/*
+ * CMSIS-Core(M) Level 1 Cache API for Armv7-M and later
+ */
+
+#ifndef ARM_ARMV7M_CACHEL1_H
+#define ARM_ARMV7M_CACHEL1_H
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header    /* treat file as system include file */
+#endif
+
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_CacheFunctions Cache Functions
+  \brief    Functions that configure Instruction and Data cache.
+  @{
+ */
+
+/* Cache Size ID Register Macros */
+#define CCSIDR_WAYS(x)         (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos)
+#define CCSIDR_SETS(x)         (((x) & SCB_CCSIDR_NUMSETS_Msk      ) >> SCB_CCSIDR_NUMSETS_Pos      )
+
+#ifndef __SCB_DCACHE_LINE_SIZE
+#define __SCB_DCACHE_LINE_SIZE  32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */
+#endif
+
+#ifndef __SCB_ICACHE_LINE_SIZE
+#define __SCB_ICACHE_LINE_SIZE  32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */
+#endif
+
+/**
+  \brief   Enable I-Cache
+  \details Turns on I-Cache
+  */
+__STATIC_FORCEINLINE void SCB_EnableICache (void)
+{
+  #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
+    if (SCB->CCR & SCB_CCR_IC_Msk) return;  /* return if ICache is already enabled */
+
+    __DSB();
+    __ISB();
+    SCB->ICIALLU = 0UL;                     /* invalidate I-Cache */
+    __DSB();
+    __ISB();
+    SCB->CCR |=  (uint32_t)SCB_CCR_IC_Msk;  /* enable I-Cache */
+    __DSB();
+    __ISB();
+  #endif
+}
+
+
+/**
+  \brief   Disable I-Cache
+  \details Turns off I-Cache
+  */
+__STATIC_FORCEINLINE void SCB_DisableICache (void)
+{
+  #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
+    __DSB();
+    __ISB();
+    SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk;  /* disable I-Cache */
+    SCB->ICIALLU = 0UL;                     /* invalidate I-Cache */
+    __DSB();
+    __ISB();
+  #endif
+}
+
+
+/**
+  \brief   Invalidate I-Cache
+  \details Invalidates I-Cache
+  */
+__STATIC_FORCEINLINE void SCB_InvalidateICache (void)
+{
+  #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
+    __DSB();
+    __ISB();
+    SCB->ICIALLU = 0UL;
+    __DSB();
+    __ISB();
+  #endif
+}
+
+
+/**
+  \brief   I-Cache Invalidate by address
+  \details Invalidates I-Cache for the given address.
+           I-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity.
+           I-Cache memory blocks which are part of given address + given size are invalidated.
+  \param[in]   addr    address
+  \param[in]   isize   size of memory block (in number of bytes)
+*/
+__STATIC_FORCEINLINE void SCB_InvalidateICache_by_Addr (volatile void *addr, int32_t isize)
+{
+  #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
+    if ( isize > 0 ) {
+       int32_t op_size = isize + (((uint32_t)addr) & (__SCB_ICACHE_LINE_SIZE - 1U));
+      uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_ICACHE_LINE_SIZE - 1U) */;
+
+      __DSB();
+
+      do {
+        SCB->ICIMVAU = op_addr;             /* register accepts only 32byte aligned values, only bits 31..5 are valid */
+        op_addr += __SCB_ICACHE_LINE_SIZE;
+        op_size -= __SCB_ICACHE_LINE_SIZE;
+      } while ( op_size > 0 );
+
+      __DSB();
+      __ISB();
+    }
+  #endif
+}
+
+
+/**
+  \brief   Enable D-Cache
+  \details Turns on D-Cache
+  */
+__STATIC_FORCEINLINE void SCB_EnableDCache (void)
+{
+  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+    uint32_t ccsidr;
+    uint32_t sets;
+    uint32_t ways;
+
+    if (SCB->CCR & SCB_CCR_DC_Msk) return;  /* return if DCache is already enabled */
+
+    SCB->CSSELR = 0U;                       /* select Level 1 data cache */
+    __DSB();
+
+    ccsidr = SCB->CCSIDR;
+
+                                            /* invalidate D-Cache */
+    sets = (uint32_t)(CCSIDR_SETS(ccsidr));
+    do {
+      ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
+      do {
+        SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) |
+                      ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk)  );
+        #if defined ( __CC_ARM )
+          __schedule_barrier();
+        #endif
+      } while (ways-- != 0U);
+    } while(sets-- != 0U);
+    __DSB();
+
+    SCB->CCR |=  (uint32_t)SCB_CCR_DC_Msk;  /* enable D-Cache */
+
+    __DSB();
+    __ISB();
+  #endif
+}
+
+
+/**
+  \brief   Disable D-Cache
+  \details Turns off D-Cache
+  */
+__STATIC_FORCEINLINE void SCB_DisableDCache (void)
+{
+  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+    struct {
+      uint32_t ccsidr;
+      uint32_t sets;
+      uint32_t ways;
+    } locals
+    #if ((defined(__GNUC__) || defined(__clang__)) && !defined(__OPTIMIZE__))
+       __ALIGNED(__SCB_DCACHE_LINE_SIZE)
+    #endif
+    ;
+
+    SCB->CSSELR = 0U;                       /* select Level 1 data cache */
+    __DSB();
+
+    SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk;  /* disable D-Cache */
+    __DSB();
+
+    #if !defined(__OPTIMIZE__)
+      /*
+       * For the endless loop issue with no optimization builds.
+       * More details, see https://github.com/ARM-software/CMSIS_5/issues/620
+       *
+       * The issue only happens when local variables are in stack. If
+       * local variables are saved in general purpose register, then the function
+       * is OK.
+       *
+       * When local variables are in stack, after disabling the cache, flush the
+       * local variables cache line for data consistency.
+       */
+      /* Clean and invalidate the local variable cache. */
+    #if defined(__ICCARM__)
+    /* As we can't align the stack to the cache line size, invalidate each of the variables */
+      SCB->DCCIMVAC = (uint32_t)&locals.sets;
+      SCB->DCCIMVAC = (uint32_t)&locals.ways;
+      SCB->DCCIMVAC = (uint32_t)&locals.ccsidr;
+    #else
+      SCB->DCCIMVAC = (uint32_t)&locals;
+    #endif
+      __DSB();
+      __ISB();
+    #endif
+
+    locals.ccsidr = SCB->CCSIDR;
+                                            /* clean & invalidate D-Cache */
+    locals.sets = (uint32_t)(CCSIDR_SETS(locals.ccsidr));
+    do {
+      locals.ways = (uint32_t)(CCSIDR_WAYS(locals.ccsidr));
+      do {
+        SCB->DCCISW = (((locals.sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) |
+                       ((locals.ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk)  );
+        #if defined ( __CC_ARM )
+          __schedule_barrier();
+        #endif
+      } while (locals.ways-- != 0U);
+    } while(locals.sets-- != 0U);
+
+    __DSB();
+    __ISB();
+  #endif
+}
+
+
+/**
+  \brief   Invalidate D-Cache
+  \details Invalidates D-Cache
+  */
+__STATIC_FORCEINLINE void SCB_InvalidateDCache (void)
+{
+  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+    uint32_t ccsidr;
+    uint32_t sets;
+    uint32_t ways;
+
+    SCB->CSSELR = 0U;                       /* select Level 1 data cache */
+    __DSB();
+
+    ccsidr = SCB->CCSIDR;
+
+                                            /* invalidate D-Cache */
+    sets = (uint32_t)(CCSIDR_SETS(ccsidr));
+    do {
+      ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
+      do {
+        SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) |
+                      ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk)  );
+        #if defined ( __CC_ARM )
+          __schedule_barrier();
+        #endif
+      } while (ways-- != 0U);
+    } while(sets-- != 0U);
+
+    __DSB();
+    __ISB();
+  #endif
+}
+
+
+/**
+  \brief   Clean D-Cache
+  \details Cleans D-Cache
+  */
+__STATIC_FORCEINLINE void SCB_CleanDCache (void)
+{
+  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+    uint32_t ccsidr;
+    uint32_t sets;
+    uint32_t ways;
+
+    SCB->CSSELR = 0U;                       /* select Level 1 data cache */
+    __DSB();
+
+    ccsidr = SCB->CCSIDR;
+
+                                            /* clean D-Cache */
+    sets = (uint32_t)(CCSIDR_SETS(ccsidr));
+    do {
+      ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
+      do {
+        SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) |
+                      ((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk)  );
+        #if defined ( __CC_ARM )
+          __schedule_barrier();
+        #endif
+      } while (ways-- != 0U);
+    } while(sets-- != 0U);
+
+    __DSB();
+    __ISB();
+  #endif
+}
+
+
+/**
+  \brief   Clean & Invalidate D-Cache
+  \details Cleans and Invalidates D-Cache
+  */
+__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache (void)
+{
+  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+    uint32_t ccsidr;
+    uint32_t sets;
+    uint32_t ways;
+
+    SCB->CSSELR = 0U;                       /* select Level 1 data cache */
+    __DSB();
+
+    ccsidr = SCB->CCSIDR;
+
+                                            /* clean & invalidate D-Cache */
+    sets = (uint32_t)(CCSIDR_SETS(ccsidr));
+    do {
+      ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
+      do {
+        SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) |
+                       ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk)  );
+        #if defined ( __CC_ARM )
+          __schedule_barrier();
+        #endif
+      } while (ways-- != 0U);
+    } while(sets-- != 0U);
+
+    __DSB();
+    __ISB();
+  #endif
+}
+
+
+/**
+  \brief   D-Cache Invalidate by address
+  \details Invalidates D-Cache for the given address.
+           D-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity.
+           D-Cache memory blocks which are part of given address + given size are invalidated.
+  \param[in]   addr    address
+  \param[in]   dsize   size of memory block (in number of bytes)
+*/
+__STATIC_FORCEINLINE void SCB_InvalidateDCache_by_Addr (volatile void *addr, int32_t dsize)
+{
+  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+    if ( dsize > 0 ) {
+       int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U));
+      uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */;
+
+      __DSB();
+
+      do {
+        SCB->DCIMVAC = op_addr;             /* register accepts only 32byte aligned values, only bits 31..5 are valid */
+        op_addr += __SCB_DCACHE_LINE_SIZE;
+        op_size -= __SCB_DCACHE_LINE_SIZE;
+      } while ( op_size > 0 );
+
+      __DSB();
+      __ISB();
+    }
+  #endif
+}
+
+
+/**
+  \brief   D-Cache Clean by address
+  \details Cleans D-Cache for the given address
+           D-Cache is cleaned starting from a 32 byte aligned address in 32 byte granularity.
+           D-Cache memory blocks which are part of given address + given size are cleaned.
+  \param[in]   addr    address
+  \param[in]   dsize   size of memory block (in number of bytes)
+*/
+__STATIC_FORCEINLINE void SCB_CleanDCache_by_Addr (volatile void *addr, int32_t dsize)
+{
+  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+    if ( dsize > 0 ) {
+       int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U));
+      uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */;
+
+      __DSB();
+
+      do {
+        SCB->DCCMVAC = op_addr;             /* register accepts only 32byte aligned values, only bits 31..5 are valid */
+        op_addr += __SCB_DCACHE_LINE_SIZE;
+        op_size -= __SCB_DCACHE_LINE_SIZE;
+      } while ( op_size > 0 );
+
+      __DSB();
+      __ISB();
+    }
+  #endif
+}
+
+
+/**
+  \brief   D-Cache Clean and Invalidate by address
+  \details Cleans and invalidates D_Cache for the given address
+           D-Cache is cleaned and invalidated starting from a 32 byte aligned address in 32 byte granularity.
+           D-Cache memory blocks which are part of given address + given size are cleaned and invalidated.
+  \param[in]   addr    address (aligned to 32-byte boundary)
+  \param[in]   dsize   size of memory block (in number of bytes)
+*/
+__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache_by_Addr (volatile void *addr, int32_t dsize)
+{
+  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+    if ( dsize > 0 ) {
+       int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U));
+      uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */;
+
+      __DSB();
+
+      do {
+        SCB->DCCIMVAC = op_addr;            /* register accepts only 32byte aligned values, only bits 31..5 are valid */
+        op_addr +=          __SCB_DCACHE_LINE_SIZE;
+        op_size -=          __SCB_DCACHE_LINE_SIZE;
+      } while ( op_size > 0 );
+
+      __DSB();
+      __ISB();
+    }
+  #endif
+}
+
+/*@} end of CMSIS_Core_CacheFunctions */
+
+#endif /* ARM_ARMV7M_CACHEL1_H */

include/cmsis/m-profile/armv7m_mpu.h

@@ -0,0 +1,273 @@
+/*
+ * Copyright (c) 2017-2020 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/*
+ * CMSIS-Core(M) MPU API for Armv7-M MPU
+ */
+
+#ifndef ARM_MPU_ARMV7_H
+#define ARM_MPU_ARMV7_H
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header    /* treat file as system include file */
+#endif
+
+#define ARM_MPU_REGION_SIZE_32B      ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes
+#define ARM_MPU_REGION_SIZE_64B      ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes
+#define ARM_MPU_REGION_SIZE_128B     ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes
+#define ARM_MPU_REGION_SIZE_256B     ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes
+#define ARM_MPU_REGION_SIZE_512B     ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes
+#define ARM_MPU_REGION_SIZE_1KB      ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte
+#define ARM_MPU_REGION_SIZE_2KB      ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes
+#define ARM_MPU_REGION_SIZE_4KB      ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes
+#define ARM_MPU_REGION_SIZE_8KB      ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes
+#define ARM_MPU_REGION_SIZE_16KB     ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes
+#define ARM_MPU_REGION_SIZE_32KB     ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes
+#define ARM_MPU_REGION_SIZE_64KB     ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes
+#define ARM_MPU_REGION_SIZE_128KB    ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes
+#define ARM_MPU_REGION_SIZE_256KB    ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes
+#define ARM_MPU_REGION_SIZE_512KB    ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes
+#define ARM_MPU_REGION_SIZE_1MB      ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte
+#define ARM_MPU_REGION_SIZE_2MB      ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes
+#define ARM_MPU_REGION_SIZE_4MB      ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes
+#define ARM_MPU_REGION_SIZE_8MB      ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes
+#define ARM_MPU_REGION_SIZE_16MB     ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes
+#define ARM_MPU_REGION_SIZE_32MB     ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes
+#define ARM_MPU_REGION_SIZE_64MB     ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes
+#define ARM_MPU_REGION_SIZE_128MB    ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes
+#define ARM_MPU_REGION_SIZE_256MB    ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes
+#define ARM_MPU_REGION_SIZE_512MB    ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes
+#define ARM_MPU_REGION_SIZE_1GB      ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte
+#define ARM_MPU_REGION_SIZE_2GB      ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes
+#define ARM_MPU_REGION_SIZE_4GB      ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes
+
+#define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access
+#define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only
+#define ARM_MPU_AP_URO  2U ///!< MPU Access Permission unprivileged access read-only
+#define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access
+#define ARM_MPU_AP_PRO  5U ///!< MPU Access Permission privileged access read-only
+#define ARM_MPU_AP_RO   6U ///!< MPU Access Permission read-only access
+
+/** MPU Region Base Address Register Value
+*
+* \param Region The region to be configured, number 0 to 15.
+* \param BaseAddress The base address for the region.
+*/
+#define ARM_MPU_RBAR(Region, BaseAddress) \
+  (((BaseAddress) & MPU_RBAR_ADDR_Msk) |  \
+   ((Region) & MPU_RBAR_REGION_Msk)    |  \
+   (MPU_RBAR_VALID_Msk))
+
+/**
+* MPU Memory Access Attributes
+*
+* \param TypeExtField      Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
+* \param IsShareable       Region is shareable between multiple bus masters.
+* \param IsCacheable       Region is cacheable, i.e. its value may be kept in cache.
+* \param IsBufferable      Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
+*/
+#define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable)   \
+  ((((TypeExtField) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk)                  | \
+   (((IsShareable)  << MPU_RASR_S_Pos)   & MPU_RASR_S_Msk)                    | \
+   (((IsCacheable)  << MPU_RASR_C_Pos)   & MPU_RASR_C_Msk)                    | \
+   (((IsBufferable) << MPU_RASR_B_Pos)   & MPU_RASR_B_Msk))
+
+/**
+* MPU Region Attribute and Size Register Value
+*
+* \param DisableExec       Instruction access disable bit, 1= disable instruction fetches.
+* \param AccessPermission  Data access permissions, allows you to configure read/write access for User and Privileged mode.
+* \param AccessAttributes  Memory access attribution, see \ref ARM_MPU_ACCESS_.
+* \param SubRegionDisable  Sub-region disable field.
+* \param Size              Region size of the region to be configured, for example 4K, 8K.
+*/
+#define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size)    \
+  ((((DisableExec)      << MPU_RASR_XN_Pos)   & MPU_RASR_XN_Msk)                                  | \
+   (((AccessPermission) << MPU_RASR_AP_Pos)   & MPU_RASR_AP_Msk)                                  | \
+   (((AccessAttributes) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk))) | \
+   (((SubRegionDisable) << MPU_RASR_SRD_Pos)  & MPU_RASR_SRD_Msk)                                 | \
+   (((Size)             << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk)                                | \
+   (((MPU_RASR_ENABLE_Msk))))
+
+/**
+* MPU Region Attribute and Size Register Value
+*
+* \param DisableExec       Instruction access disable bit, 1= disable instruction fetches.
+* \param AccessPermission  Data access permissions, allows you to configure read/write access for User and Privileged mode.
+* \param TypeExtField      Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
+* \param IsShareable       Region is shareable between multiple bus masters.
+* \param IsCacheable       Region is cacheable, i.e. its value may be kept in cache.
+* \param IsBufferable      Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
+* \param SubRegionDisable  Sub-region disable field.
+* \param Size              Region size of the region to be configured, for example 4K, 8K.
+*/
+#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \
+  ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size)
+
+/**
+* MPU Memory Access Attribute for strongly ordered memory.
+*  - TEX: 000b
+*  - Shareable
+*  - Non-cacheable
+*  - Non-bufferable
+*/
+#define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U)
+
+/**
+* MPU Memory Access Attribute for device memory.
+*  - TEX: 000b (if shareable) or 010b (if non-shareable)
+*  - Shareable or non-shareable
+*  - Non-cacheable
+*  - Bufferable (if shareable) or non-bufferable (if non-shareable)
+*
+* \param IsShareable Configures the device memory as shareable or non-shareable.
+*/
+#define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U))
+
+/**
+* MPU Memory Access Attribute for normal memory.
+*  - TEX: 1BBb (reflecting outer cacheability rules)
+*  - Shareable or non-shareable
+*  - Cacheable or non-cacheable (reflecting inner cacheability rules)
+*  - Bufferable or non-bufferable (reflecting inner cacheability rules)
+*
+* \param OuterCp Configures the outer cache policy.
+* \param InnerCp Configures the inner cache policy.
+* \param IsShareable Configures the memory as shareable or non-shareable.
+*/
+#define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) >> 1U), ((InnerCp) & 1U))
+
+/**
+* MPU Memory Access Attribute non-cacheable policy.
+*/
+#define ARM_MPU_CACHEP_NOCACHE 0U
+
+/**
+* MPU Memory Access Attribute write-back, write and read allocate policy.
+*/
+#define ARM_MPU_CACHEP_WB_WRA 1U
+
+/**
+* MPU Memory Access Attribute write-through, no write allocate policy.
+*/
+#define ARM_MPU_CACHEP_WT_NWA 2U
+
+/**
+* MPU Memory Access Attribute write-back, no write allocate policy.
+*/
+#define ARM_MPU_CACHEP_WB_NWA 3U
+
+
+/**
+* Struct for a single MPU Region
+*/
+typedef struct {
+  uint32_t RBAR; //!< The region base address register value (RBAR)
+  uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR
+} ARM_MPU_Region_t;
+
+/** Enable the MPU.
+* \param MPU_Control Default access permissions for unconfigured regions.
+*/
+__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
+{
+  __DMB();
+  MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk
+  SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
+#endif
+  __DSB();
+  __ISB();
+}
+
+/** Disable the MPU.
+*/
+__STATIC_INLINE void ARM_MPU_Disable(void)
+{
+  __DMB();
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk
+  SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
+#endif
+  MPU->CTRL  &= ~MPU_CTRL_ENABLE_Msk;
+  __DSB();
+  __ISB();
+}
+
+/** Clear and disable the given MPU region.
+* \param rnr Region number to be cleared.
+*/
+__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
+{
+  MPU->RNR = rnr;
+  MPU->RASR = 0U;
+}
+
+/** Configure an MPU region.
+* \param rbar Value for RBAR register.
+* \param rasr Value for RASR register.
+*/
+__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr)
+{
+  MPU->RBAR = rbar;
+  MPU->RASR = rasr;
+}
+
+/** Configure the given MPU region.
+* \param rnr Region number to be configured.
+* \param rbar Value for RBAR register.
+* \param rasr Value for RASR register.
+*/
+__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr)
+{
+  MPU->RNR = rnr;
+  MPU->RBAR = rbar;
+  MPU->RASR = rasr;
+}
+
+/** Memcpy with strictly ordered memory access, e.g. used by code in ARM_MPU_Load().
+* \param dst Destination data is copied to.
+* \param src Source data is copied from.
+* \param len Amount of data words to be copied.
+*/
+__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
+{
+  uint32_t i;
+  for (i = 0U; i < len; ++i)
+  {
+    dst[i] = src[i];
+  }
+}
+
+/** Load the given number of MPU regions from a table.
+* \param table Pointer to the MPU configuration table.
+* \param cnt Amount of regions to be configured.
+*/
+__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt)
+{
+  const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
+  while (cnt > MPU_TYPE_RALIASES) {
+    ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize);
+    table += MPU_TYPE_RALIASES;
+    cnt -= MPU_TYPE_RALIASES;
+  }
+  ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize);
+}
+
+#endif

include/cmsis/m-profile/cmsis_gcc_m.h

@@ -0,0 +1,716 @@
+/*
+ * Copyright (c) 2009-2023 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/*
+ * CMSIS-Core(M) Compiler GCC Header File
+ */
+
+#ifndef __CMSIS_GCC_M_H
+#define __CMSIS_GCC_M_H
+
+#ifndef __CMSIS_GCC_H
+  #error "This file must not be included directly"
+#endif
+
+#include <arm_acle.h>
+
+/* #########################  Startup and Lowlevel Init  ######################## */
+#ifndef __PROGRAM_START
+
+/**
+  \brief   Initializes data and bss sections
+  \details This default implementations initialized all data and additional bss
+           sections relying on .copy.table and .zero.table specified properly
+           in the used linker script.
+
+ */
+__STATIC_FORCEINLINE __NO_RETURN void __cmsis_start(void)
+{
+  extern void _start(void) __NO_RETURN;
+
+  typedef struct __copy_table {
+    uint32_t const* src;
+    uint32_t* dest;
+    uint32_t  wlen;
+  } __copy_table_t;
+
+  typedef struct __zero_table {
+    uint32_t* dest;
+    uint32_t  wlen;
+  } __zero_table_t;
+
+  extern const __copy_table_t __copy_table_start__;
+  extern const __copy_table_t __copy_table_end__;
+  extern const __zero_table_t __zero_table_start__;
+  extern const __zero_table_t __zero_table_end__;
+
+  for (__copy_table_t const* pTable = &__copy_table_start__; pTable < &__copy_table_end__; ++pTable) {
+    for(uint32_t i=0u; i<pTable->wlen; ++i) {
+      pTable->dest[i] = pTable->src[i];
+    }
+  }
+
+  for (__zero_table_t const* pTable = &__zero_table_start__; pTable < &__zero_table_end__; ++pTable) {
+    for(uint32_t i=0u; i<pTable->wlen; ++i) {
+      pTable->dest[i] = 0u;
+    }
+  }
+
+  _start();
+}
+
+#define __PROGRAM_START           __cmsis_start
+#endif
+
+#ifndef __INITIAL_SP
+#define __INITIAL_SP              __StackTop
+#endif
+
+#ifndef __STACK_LIMIT
+#define __STACK_LIMIT             __StackLimit
+#endif
+
+#ifndef __VECTOR_TABLE
+#define __VECTOR_TABLE            __Vectors
+#endif
+
+#ifndef __VECTOR_TABLE_ATTRIBUTE
+#define __VECTOR_TABLE_ATTRIBUTE  __attribute__((used, section(".vectors")))
+#endif
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)
+#ifndef __STACK_SEAL
+#define __STACK_SEAL              __StackSeal
+#endif
+
+#ifndef __TZ_STACK_SEAL_SIZE
+#define __TZ_STACK_SEAL_SIZE      8U
+#endif
+
+#ifndef __TZ_STACK_SEAL_VALUE
+#define __TZ_STACK_SEAL_VALUE     0xFEF5EDA5FEF5EDA5ULL
+#endif
+
+__STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop)
+{
+  *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE;
+}
+#endif
+
+
+/* ###########################  Core Function Access  ########################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+  @{
+ */
+
+/**
+  \brief   Get Control Register
+  \details Returns the content of the Control Register.
+  \return               Control Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_CONTROL(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, control" : "=r" (result) );
+  return (result);
+}
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)
+/**
+  \brief   Get Control Register (non-secure)
+  \details Returns the content of the non-secure Control Register when in secure mode.
+  \return               non-secure Control Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, control_ns" : "=r" (result) );
+  return (result);
+}
+#endif
+
+
+/**
+  \brief   Set Control Register
+  \details Writes the given value to the Control Register.
+  \param [in]    control  Control Register value to set
+ */
+__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control)
+{
+  __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
+  __ISB();
+}
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)
+/**
+  \brief   Set Control Register (non-secure)
+  \details Writes the given value to the non-secure Control Register when in secure state.
+  \param [in]    control  Control Register value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control)
+{
+  __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory");
+  __ISB();
+}
+#endif
+
+
+/**
+  \brief   Get IPSR Register
+  \details Returns the content of the IPSR Register.
+  \return               IPSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_IPSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
+  return (result);
+}
+
+
+/**
+  \brief   Get APSR Register
+  \details Returns the content of the APSR Register.
+  \return               APSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_APSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, apsr" : "=r" (result) );
+  return (result);
+}
+
+
+/**
+  \brief   Get xPSR Register
+  \details Returns the content of the xPSR Register.
+  \return               xPSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_xPSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
+  return (result);
+}
+
+
+/**
+  \brief   Get Process Stack Pointer
+  \details Returns the current value of the Process Stack Pointer (PSP).
+  \return               PSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PSP(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, psp"  : "=r" (result) );
+  return (result);
+}
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)
+/**
+  \brief   Get Process Stack Pointer (non-secure)
+  \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state.
+  \return               PSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, psp_ns"  : "=r" (result) );
+  return (result);
+}
+#endif
+
+
+/**
+  \brief   Set Process Stack Pointer
+  \details Assigns the given value to the Process Stack Pointer (PSP).
+  \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack)
+{
+  __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : );
+}
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)
+/**
+  \brief   Set Process Stack Pointer (non-secure)
+  \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state.
+  \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)
+{
+  __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : );
+}
+#endif
+
+
+/**
+  \brief   Get Main Stack Pointer
+  \details Returns the current value of the Main Stack Pointer (MSP).
+  \return               MSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_MSP(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, msp" : "=r" (result) );
+  return (result);
+}
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)
+/**
+  \brief   Get Main Stack Pointer (non-secure)
+  \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state.
+  \return               MSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, msp_ns" : "=r" (result) );
+  return (result);
+}
+#endif
+
+
+/**
+  \brief   Set Main Stack Pointer
+  \details Assigns the given value to the Main Stack Pointer (MSP).
+  \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack)
+{
+  __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );
+}
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)
+/**
+  \brief   Set Main Stack Pointer (non-secure)
+  \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.
+  \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)
+{
+  __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : );
+}
+#endif
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)
+/**
+  \brief   Get Stack Pointer (non-secure)
+  \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state.
+  \return               SP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, sp_ns" : "=r" (result) );
+  return (result);
+}
+
+
+/**
+  \brief   Set Stack Pointer (non-secure)
+  \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state.
+  \param [in]    topOfStack  Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack)
+{
+  __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : );
+}
+#endif
+
+
+/**
+  \brief   Get Priority Mask
+  \details Returns the current state of the priority mask bit from the Priority Mask Register.
+  \return               Priority Mask value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, primask" : "=r" (result) );
+  return (result);
+}
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)
+/**
+  \brief   Get Priority Mask (non-secure)
+  \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state.
+  \return               Priority Mask value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, primask_ns" : "=r" (result) );
+  return (result);
+}
+#endif
+
+
+/**
+  \brief   Set Priority Mask
+  \details Assigns the given value to the Priority Mask Register.
+  \param [in]    priMask  Priority Mask
+ */
+__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask)
+{
+  __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+}
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)
+/**
+  \brief   Set Priority Mask (non-secure)
+  \details Assigns the given value to the non-secure Priority Mask Register when in secure state.
+  \param [in]    priMask  Priority Mask
+ */
+__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)
+{
+  __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory");
+}
+#endif
+
+
+#if (__ARM_ARCH_ISA_THUMB >= 2)
+/**
+  \brief   Get Base Priority
+  \details Returns the current value of the Base Priority register.
+  \return               Base Priority register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, basepri" : "=r" (result) );
+  return (result);
+}
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)
+/**
+  \brief   Get Base Priority (non-secure)
+  \details Returns the current value of the non-secure Base Priority register when in secure state.
+  \return               Base Priority register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) );
+  return (result);
+}
+#endif
+
+
+/**
+  \brief   Set Base Priority
+  \details Assigns the given value to the Base Priority register.
+  \param [in]    basePri  Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri)
+{
+  __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory");
+}
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)
+/**
+  \brief   Set Base Priority (non-secure)
+  \details Assigns the given value to the non-secure Base Priority register when in secure state.
+  \param [in]    basePri  Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri)
+{
+  __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory");
+}
+#endif
+
+
+/**
+  \brief   Set Base Priority with condition
+  \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
+           or the new value increases the BASEPRI priority level.
+  \param [in]    basePri  Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri)
+{
+  __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory");
+}
+
+
+/**
+  \brief   Get Fault Mask
+  \details Returns the current value of the Fault Mask register.
+  \return               Fault Mask register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
+  return (result);
+}
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)
+/**
+  \brief   Get Fault Mask (non-secure)
+  \details Returns the current value of the non-secure Fault Mask register when in secure state.
+  \return               Fault Mask register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) );
+  return (result);
+}
+#endif
+
+
+/**
+  \brief   Set Fault Mask
+  \details Assigns the given value to the Fault Mask register.
+  \param [in]    faultMask  Fault Mask value to set
+ */
+__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+  __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
+}
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)
+/**
+  \brief   Set Fault Mask (non-secure)
+  \details Assigns the given value to the non-secure Fault Mask register when in secure state.
+  \param [in]    faultMask  Fault Mask value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)
+{
+  __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory");
+}
+#endif
+
+#endif /* (__ARM_ARCH_ISA_THUMB >= 2) */
+
+
+#if (__ARM_ARCH >= 8)
+/**
+  \brief   Get Process Stack Pointer Limit
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence zero is returned always in non-secure
+  mode.
+
+  \details Returns the current value of the Process Stack Pointer Limit (PSPLIM).
+  \return               PSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+     !(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) && \
+     (!defined (__ARM_FEATURE_CMSE  ) || (__ARM_FEATURE_CMSE   < 3)))
+  /* without main extensions, the non-secure PSPLIM is RAZ/WI */
+  return (0U);
+#else
+  uint32_t result;
+  __ASM volatile ("MRS %0, psplim"  : "=r" (result) );
+  return (result);
+#endif
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)
+/**
+  \brief   Get Process Stack Pointer Limit (non-secure)
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence zero is returned always.
+
+  \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
+  \return               PSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+     !(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)))
+  /* without main extensions, the non-secure PSPLIM is RAZ/WI */
+  return (0U);
+#else
+  uint32_t result;
+  __ASM volatile ("MRS %0, psplim_ns"  : "=r" (result) );
+  return (result);
+#endif
+}
+#endif
+
+
+/**
+  \brief   Set Process Stack Pointer Limit
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence the write is silently ignored in non-secure
+  mode.
+
+  \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).
+  \param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+     !(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) && \
+     (!defined (__ARM_FEATURE_CMSE  ) || (__ARM_FEATURE_CMSE   < 3)))
+  /* without main extensions, the non-secure PSPLIM is RAZ/WI */
+  (void)ProcStackPtrLimit;
+#else
+  __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));
+#endif
+}
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)
+/**
+  \brief   Set Process Stack Pointer (non-secure)
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence the write is silently ignored.
+
+  \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
+  \param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+     !(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)))
+  /* without main extensions, the non-secure PSPLIM is RAZ/WI */
+  (void)ProcStackPtrLimit;
+#else
+  __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit));
+#endif
+}
+#endif
+
+
+/**
+  \brief   Get Main Stack Pointer Limit
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence zero is returned always.
+
+  \details Returns the current value of the Main Stack Pointer Limit (MSPLIM).
+  \return               MSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+     !(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) && \
+     (!defined (__ARM_FEATURE_CMSE  ) || (__ARM_FEATURE_CMSE   < 3)))
+  /* without main extensions, the non-secure MSPLIM is RAZ/WI */
+  return (0U);
+#else
+  uint32_t result;
+  __ASM volatile ("MRS %0, msplim" : "=r" (result) );
+  return (result);
+#endif
+}
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)
+/**
+  \brief   Get Main Stack Pointer Limit (non-secure)
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence zero is returned always.
+
+  \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state.
+  \return               MSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+     !(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)))
+  /* without main extensions, the non-secure MSPLIM is RAZ/WI */
+  return (0U);
+#else
+  uint32_t result;
+  __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) );
+  return (result);
+#endif
+}
+#endif
+
+
+/**
+  \brief   Set Main Stack Pointer Limit
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence the write is silently ignored.
+
+  \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).
+  \param [in]    MainStackPtrLimit  Main Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+     !(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) && \
+     (!defined (__ARM_FEATURE_CMSE  ) || (__ARM_FEATURE_CMSE   < 3)))
+  /* without main extensions, the non-secure MSPLIM is RAZ/WI */
+  (void)MainStackPtrLimit;
+#else
+  __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));
+#endif
+}
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)
+/**
+  \brief   Set Main Stack Pointer Limit (non-secure)
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence the write is silently ignored.
+
+  \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state.
+  \param [in]    MainStackPtrLimit  Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+     !(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)))
+  /* without main extensions, the non-secure MSPLIM is RAZ/WI */
+  (void)MainStackPtrLimit;
+#else
+  __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit));
+#endif
+}
+#endif
+
+#endif /* (__ARM_ARCH >= 8) */
+/** @} end of CMSIS_Core_RegAccFunctions */
+
+#endif /* __CMSIS_GCC_M_H */

include/rtl8710bx.h

@@ -0,0 +1,985 @@
+#ifndef RTL8710BX_H
+#define RTL8710BX_H
+
+typedef enum IRQn {
+  Reset_IRQn = -15, /* Reset Vector, invoked on Power up and warm reset */
+  NonMaskableInt_IRQn =
+      -14, /* Non maskable Interrupt, cannot be stopped or preempted */
+  HardFault_IRQn = -13,        /* Hard Fault, all classes of Fault */
+  MemoryManagement_IRQn = -12, /* Memory Management, MPU mismatch, including
+                                  Access Violation and No Match */
+  BusFault_IRQn = -11,         /* Bus Fault, Pre-Fetch-, Memory Access, other
+                                  address/memory Fault */
+  UsageFault_IRQn =
+      -10, /* Usage Fault, i.e. Undef Instruction, Illegal State Transition */
+  SecureFault_IRQn = -9,  /* Secure Fault Interrupt */
+  SVCall_IRQn = -5,       /* System Service Call via SVC instruction */
+  DebugMonitor_IRQn = -4, /* Debug Monitor */
+  PendSV_IRQn = -2,       /* Pendable request for system service */
+  SysTick_IRQn = -1,      /* System Tick Timer */
+
+  /* RTL8710BX specific interrupts */
+  PWR_Wakeup_IRQn = 0,     /* System wakeup from power save interrupt */
+  WDG_IRQn = 1,            /* Window watchdog interrupt */
+  TIM0_IRQn = 2,           /* Timer 0 global interrupt */
+  TIM1_IRQn = 3,           /* Timer 1 global interrupt */
+  TIM2_IRQn = 4,           /* Timer 2 global interrupt */
+  TIM3_IRQn = 5,           /* Timer 3 global interrupt */
+  SPI0_IRQn = 6,           /* SPI0 global interrupt */
+  GPIO_IRQn = 7,           /* GPIO global interrupt */
+  UART0_IRQn = 8,          /* UART0 global interrupt */
+  FLASH_IRQn = 9,          /* Flash memory global interrupt */
+  UART1_IRQn = 10,         /* UART1 global interrupt */
+  TIM4_IRQn = 11,          /* Timer 4 global interrupt */
+  SDIO_IRQn = 12,          /* SDIO global interrupt */
+  I2S0_PCM0_IRQn = 13,     /* I2S0/PCM0 global interrupt */
+  TIM5_IRQn = 14,          /* Timer 5 global interrupt */
+  WLAN_DMA_IRQn = 15,      /* WLAN DMA global interrupt */
+  WLAN_Protocol_IRQn = 16, /* WLAN protocol global interrupt */
+  Crypto_IRQn = 17,        /* Cryptography global interrupt */
+  SPI1_IRQn = 18,          /* SPI1 global interrupt */
+  Periph_IRQn = 19,        /* Peripheral global interrupt */
+  DMA0_Channel0_IRQn = 20, /* DMA0 Channel 0 global interrupt */
+  DMA0_Channel1_IRQn = 21, /* DMA0 Channel 1 global interrupt */
+  DMA0_Channel2_IRQn = 22, /* DMA0 Channel 2 global interrupt */
+  DMA0_Channel3_IRQn = 23, /* DMA0 Channel 3 global interrupt */
+  DMA0_Channel4_IRQn = 24, /* DMA0 Channel 4 global interrupt */
+  DMA0_Channel5_IRQn = 25, /* DMA0 Channel 5 global interrupt */
+  I2C0_IRQn = 26,          /* I2C0 global interrupt */
+  I2C1_IRQn = 27,          /* I2C1 global interrupt */
+  UART_Log_IRQn = 28,      /* Log UART global interrupt */
+  ADC_IRQn = 29,           /* ADC global interrupt */
+  RDP_IRQn = 30,           /* CPU RDP protection interrupt */
+  RTC_IRQn = 31,           /* RTC global interrupt */
+  DMA1_Channel0_IRQn = 32, /* DMA1 Channel 0 global interrupt */
+  DMA1_Channel1_IRQn = 33, /* DMA1 Channel 1 global interrupt */
+  DMA1_Channel2_IRQn = 34, /* DMA1 Channel 2 global interrupt */
+  DMA1_Channel3_IRQn = 35, /* DMA1 Channel 3 global interrupt */
+  DMA1_Channel4_IRQn = 36, /* DMA1 Channel 4 global interrupt */
+  DMA1_Channel5_IRQn = 37, /* DMA1 Channel 5 global interrupt */
+  USB_IRQn = 38,           /* USB global interrupt */
+  RXI300_IRQn = 39,        /* RXI300 global interrupt */
+  USB_SIE_IRQn = 40,       /* USB SIE global interrupt */
+} IRQn_Type;
+
+#define __CM4_REV 0x0101          /* Core Revision r0p1 */
+#define __Vendor_SysTickConfig 0U /* Standard ARM SysTick implementation */
+#define __NVIC_PRIO_BITS 4U    /* Cortex-M4 uses 4 bits for priority levels */
+#define __VTOR_PRESENT 1U      /* Vector Table Offset Register is present */
+#define __MPU_PRESENT 1U       /* Memory Protection Unit is present */
+#define __FPU_PRESENT 1U       /* Floating Point Unit is present on this M4 */
+#define __FPU_DP 0U            /* Single-precision FPU */
+#define __DSP_PRESENT 1U       /* DSP extensions are present on M4 */
+#define __SAUREGION_PRESENT 0U /* No Security Attribution Unit */
+#define __PMU_PRESENT 0U       /* No Performance Monitoring Unit */
+#define __PMU_NUM_EVENTCNT 0U  /* Not applicable since no PMU */
+#define __ICACHE_PRESENT 0U    /* No instruction cache */
+#define __DCACHE_PRESENT 0U    /* No data cache */
+#define __DTCM_PRESENT 0U      /* No DTCM */
+
+#include "cmsis/core_cm4.h"
+
+/* Device Specific Peripheral Section */
+
+/* AMEBAZ_UART */
+typedef struct {
+  __IO uint32_t DLL;       /* Divisor Latch (unused in Amebaz) */
+  __IO uint32_t DLH_INTCR; /* Interrupt Enable */
+  __IO uint32_t INTID;     /* Interrupt Identification */
+  __IO uint32_t LCR;       /* Line Control */
+  __IO uint32_t MCR;       /* Modem Control */
+  __I uint32_t LSR;        /* Line Status */
+  __I uint32_t MDSR;       /* Modem Status */
+  __IO uint32_t SPR;       /* Scratch Pad */
+  __IO uint32_t STSR;      /* STS Register */
+  __IO uint32_t RB_THR;    /* Receive Buffer/Transmit Holding */
+  __IO uint32_t MISCR;     /* Misc Control */
+  __IO uint32_t TXPLSR;    /* IrDA TX Pulse Width Control */
+
+  __IO uint32_t RXPLSR;   /* IrDA RX Pulse Width Control */
+  __IO uint32_t BAUDMONR; /* Baud Monitor */
+  __IO uint32_t RSVD2;    /* Reserved */
+  __IO uint32_t DBG_UART; /* Debug */
+
+  /* Power save features */
+  __IO uint32_t RX_PATH;       /* RX Path Control */
+  __IO uint32_t MON_BAUD_CTRL; /* Monitor Baud Rate Control */
+  __IO uint32_t MON_BAUD_STS;  /* Monitor Baud Rate Status */
+  __IO uint32_t MON_CYC_NUM;   /* Monitor Cycle Number */
+  __IO uint32_t RX_BYTE_CNT;   /* RX Byte Counter */
+
+  __IO uint32_t FCR; /* FIFO Control */
+} UART_TypeDef;
+/** @} */
+
+/* AMEBAZ_SPI */
+typedef struct {
+  __IO uint32_t CTRLR0;          /* Control register 0 */
+  __IO uint32_t CTRLR1;          /* Control register 1 */
+  __IO uint32_t SSIENR;          /* SSI enable */
+  __IO uint32_t MWCR;            /* Microwire control */
+  __IO uint32_t SER;             /* Slave enable */
+  __IO uint32_t BAUDR;           /* Baud rate select */
+  __IO uint32_t TXFTLR;          /* TX FIFO threshold level */
+  __IO uint32_t RXFTLR;          /* RX FIFO threshold level */
+  __I uint32_t TXFLR;            /* TX FIFO level */
+  __I uint32_t RXFLR;            /* RX FIFO level */
+  __I uint32_t SR;               /* Status */
+  __IO uint32_t IMR;             /* Interrupt mask */
+  __I uint32_t ISR;              /* Interrupt status */
+  __I uint32_t RISR;             /* Raw interrupt status */
+  __I uint32_t TXOICR;           /* TX FIFO overflow interrupt clear */
+  __I uint32_t RXOICR;           /* RX FIFO overflow interrupt clear */
+  __I uint32_t RXUICR;           /* RX FIFO underflow interrupt clear */
+  __I uint32_t MSTICR;           /* Multi-master interrupt clear */
+  __I uint32_t ICR;              /* Interrupt clear */
+  __IO uint32_t DMACR;           /* DMA control */
+  __IO uint32_t DMATDLR;         /* DMA TX data level */
+  __IO uint32_t DMARDLR;         /* DMA RX data level */
+  __I uint32_t IDR;              /* Identification */
+  __I uint32_t SSI_COMP_VERSION; /* CoreKit version ID */
+  __IO uint32_t DR[36];          /* Data register array */
+  __IO uint32_t RX_SAMPLE_DLY;   /* RX sample delay */
+} SPI_TypeDef;
+/** @} */
+
+/* AMEBAZ_SPIC */
+typedef struct {
+  __IO uint32_t ctrlr0;            /* Control register 0 */
+  __IO uint32_t ctrlr1;            /* Control register 1 */
+  __IO uint32_t ssienr;            /* SPI enable */
+  __IO uint32_t mwcr;              /* Reserved */
+  __IO uint32_t ser;               /* Slave enable */
+  __IO uint32_t baudr;             /* Baudrate select */
+  __IO uint32_t txftlr;            /* TX FIFO threshold level */
+  __IO uint32_t rxftlr;            /* RX FIFO threshold level */
+  __IO uint32_t txflr;             /* TX FIFO level */
+  __IO uint32_t rxflr;             /* RX FIFO level */
+  __IO uint32_t sr;                /* Status register */
+  __IO uint32_t imr;               /* Interrupt mask */
+  __IO uint32_t isr;               /* Interrupt status */
+  __IO uint32_t risr;              /* Raw interrupt status */
+  __IO uint32_t txoicr;            /* TX FIFO overflow interrupt clear */
+  __IO uint32_t rxoicr;            /* RX FIFO overflow interrupt clear */
+  __IO uint32_t rxuicr;            /* RX FIFO underflow interrupt clear */
+  __IO uint32_t msticr;            /* Master error interrupt clear */
+  __IO uint32_t icr;               /* Interrupt clear */
+  __IO uint32_t dmacr;             /* Reserved */
+  __IO uint32_t dmatdlr;           /* Reserved */
+  __IO uint32_t dmardlr;           /* Reserved */
+  __IO uint32_t idr;               /* Identification register */
+  __IO uint32_t spi_flash_version; /* Version ID */
+  union {
+    __IO uint8_t byte;
+    __IO uint16_t half;
+    __IO uint32_t word;
+  } dr[32];                     /* Data register array */
+  __IO uint32_t rd_fast_single; /* Flash fast read command */
+  __IO uint32_t rd_dual_o;      /* Flash dual output read */
+  __IO uint32_t rd_dual_io;     /* Flash dual I/O read */
+  __IO uint32_t rd_quad_o;      /* Flash quad output read */
+  __IO uint32_t rd_quad_io;     /* Flash quad I/O read */
+  __IO uint32_t wr_single;      /* Flash page program */
+  __IO uint32_t wr_dual_i;      /* Flash dual input program */
+  __IO uint32_t wr_dual_ii;     /* Flash dual addr/data program */
+  __IO uint32_t wr_quad_i;      /* Flash quad input program */
+  __IO uint32_t wr_quad_ii;     /* Flash quad addr/data program */
+  __IO uint32_t wr_enable;      /* Flash write enable */
+  __IO uint32_t rd_status;      /* Flash read status */
+  __IO uint32_t ctrlr2;         /* Control register 2 */
+  __IO uint32_t fbaudr;         /* Fast baudrate select */
+  __IO uint32_t addr_length;    /* Address length */
+  __IO uint32_t auto_length;    /* Auto address length */
+  __IO uint32_t valid_cmd;      /* Valid command */
+  __IO uint32_t flash_size;     /* Flash size */
+  __IO uint32_t flush_fifo;     /* Flush FIFO */
+} SPIC_TypeDef;
+
+/* AMEBAZ_ADC */
+typedef struct {
+  __IO uint32_t FIFO_READ;    /* FIFO read register for channels 0-3 */
+  __IO uint32_t CONTROL;      /* Main ADC control register */
+  __IO uint32_t INTR_EN;      /* Interrupt enable register */
+  __IO uint32_t INTR_STS;     /* Interrupt status register */
+  __IO uint32_t COMP_VALUE_L; /* Compare values for channels 0-1 */
+  __IO uint32_t COMP_VALUE_H; /* Compare values for channels 2-3 */
+  __IO uint32_t COMP_SET;     /* Compare configuration register */
+  __IO uint32_t POWER;        /* Power management register */
+  __IO uint32_t ANAPAR_AD0;   /* Analog parameters for channel 0 */
+  __IO uint32_t ANAPAR_AD1;   /* Analog parameters for channel 1 */
+  __IO uint32_t ANAPAR_AD2;   /* Analog parameters for channel 2 */
+  __IO uint32_t ANAPAR_AD3;   /* Analog parameters for channel 3 */
+  __IO uint32_t ANAPAR_AD4;   /* Analog parameters for channel 4 */
+  __IO uint32_t ANAPAR_AD5;   /* Analog parameters for channel 5 */
+  __IO uint32_t CALI_DATA;    /* Calibration data register */
+} ADC_TypeDef;
+/** @} */
+
+/* AMEBAZ_I2C */
+typedef struct {
+  __IO uint32_t IC_CON;      /* Control register */
+  __IO uint32_t IC_TAR;      /* Target address register */
+  __IO uint32_t IC_SAR;      /* Slave0 address register */
+  __IO uint32_t IC_HS_MADDR; /* HS master mode code address */
+
+  __IO uint32_t IC_DATA_CMD;    /* RX/TX data buffer and command */
+  __IO uint32_t IC_SS_SCL_HCNT; /* Standard speed SCL high count */
+  __IO uint32_t IC_SS_SCL_LCNT; /* Standard speed SCL low count */
+  __IO uint32_t IC_FS_SCL_HCNT; /* Fast speed SCL high count */
+
+  __IO uint32_t IC_FS_SCL_LCNT; /* Fast speed SCL low count */
+  __IO uint32_t IC_HS_SCL_HCNT; /* High speed SCL high count */
+  __IO uint32_t IC_HS_SCL_LCNT; /* High speed SCL low count */
+  __I uint32_t IC_INTR_STAT;    /* Interrupt status */
+
+  __IO uint32_t IC_INTR_MASK;    /* Interrupt mask */
+  __I uint32_t IC_RAW_INTR_STAT; /* Raw interrupt status */
+  __IO uint32_t IC_RX_TL;        /* Receive FIFO threshold */
+  __IO uint32_t IC_TX_TL;        /* Transmit FIFO threshold */
+
+  __I uint32_t IC_CLR_INTR;     /* Clear combined interrupts */
+  __I uint32_t IC_CLR_RX_UNDER; /* Clear RX_UNDER interrupt */
+  __I uint32_t IC_CLR_RX_OVER;  /* Clear RX_OVER interrupt */
+  __I uint32_t IC_CLR_TX_OVER;  /* Clear TX_OVER interrupt */
+
+  __I uint32_t IC_CLR_RD_REQ;   /* Clear RD_REQ interrupt */
+  __I uint32_t IC_CLR_TX_ABRT;  /* Clear TX_ABRT interrupt */
+  __I uint32_t IC_CLR_RX_DONE;  /* Clear RX_DONE interrupt */
+  __I uint32_t IC_CLR_ACTIVITY; /* Clear ACTIVITY interrupt */
+
+  __I uint32_t IC_CLR_STOP_DET;  /* Clear STOP_DET interrupt */
+  __I uint32_t IC_CLR_START_DET; /* Clear START_DET interrupt */
+  __I uint32_t IC_CLR_GEN_CALL;  /* Clear GEN_CALL interrupt */
+  __IO uint32_t IC_ENABLE;       /* Enable register */
+
+  __I uint32_t IC_STATUS;    /* Status register */
+  __I uint32_t IC_TXFLR;     /* Transmit FIFO level */
+  __I uint32_t IC_RXFLR;     /* Receive FIFO level */
+  __IO uint32_t IC_SDA_HOLD; /* SDA hold time length */
+
+  __I uint32_t IC_TX_ABRT_SOURCE;      /* Transmit abort status */
+  __IO uint32_t IC_SLV_DATA_NACK_ONLY; /* Generate SLV_DATA_NACK */
+  __IO uint32_t IC_DMA_CR;             /* DMA control */
+  __IO uint32_t IC_DMA_TDLR;           /* DMA transmit data level */
+
+  __IO uint32_t IC_DMA_RDLR;         /* DMA receive data level */
+  __IO uint32_t IC_SDA_SETUP;        /* SDA setup */
+  __IO uint32_t IC_ACK_GENERAL_CALL; /* ACK general call */
+  __IO uint32_t IC_ENABLE_STATUS;    /* Enable status */
+
+  /* AmebaZ added New registers */
+  __IO uint32_t IC_DMA_CMD;     /* DMA command */
+  __IO uint32_t IC_DMA_DAT_LEN; /* DMA transmit data length */
+  __IO uint32_t IC_DMA_MOD;     /* DMA mode */
+  __IO uint32_t IC_SLEEP;       /* Sleep control */
+
+  __IO uint32_t IC_RSVD1[4]; /* Reserved field */
+  __I uint32_t IC_RSVD2[4];  /* Reserved field */
+  __I uint32_t IC_RSVD3[4];  /* Reserved field */
+
+  __I uint32_t IC_RSVD4;            /* Reserved field */
+  __I uint32_t IC_CLR_ADDR_MATCH;   /* Clear ADDR_MATCH interrupt */
+  __I uint32_t IC_CLR_DMA_I2C_DONE; /* Clear DMA_I2C_DONE interrupt */
+  __IO uint32_t IC_FILTER;          /* Filter register */
+
+  __I uint32_t IC_RSVD5;        /* Reserved field */
+  __IO uint32_t IC_SAR1;        /* Slave1 address */
+  __IO uint32_t IC_DATA_S1;     /* Slave1 RX/TX data buffer */
+  __I uint32_t IC_COMP_VERSION; /* Component version ID */
+} I2C_TypeDef;
+/** @} */
+
+/* AMEBAZ_I2S */
+typedef struct {
+  __IO uint32_t IS_CTL;         /* Main I2S control register */
+  __IO uint32_t IS_TX_PAGE_PTR; /* TX page pointer */
+  __IO uint32_t IS_RX_PAGE_PTR; /* RX page pointer */
+  __IO uint32_t IS_SETTING;     /* Page size and sample rate settings */
+
+  __IO uint32_t IS_TX_MASK_INT;   /* TX interrupt enable */
+  __IO uint32_t IS_TX_STATUS_INT; /* TX interrupt status */
+  __IO uint32_t IS_RX_MASK_INT;   /* RX interrupt enable */
+  __IO uint32_t IS_RX_STATUS_INT; /* RX interrupt status */
+
+  __IO uint32_t IS_TX_PAGE_OWN[4]; /* TX page ownership bits */
+  __IO uint32_t IS_RX_PAGE_OWN[4]; /* RX page ownership bits */
+} I2S_TypeDef;
+/** @} */
+
+/*
+ * AMEBAZ_TIMER Register Declaration
+ * TIM1 have 6 CCR registers: bit[15:0] is CCR, bit[31:24] is CCMR
+ * TIM3 have 1 CCR registesr: bit[15:0] is CCR, bit[31:24] is CCMR
+ * TIM5-8 dont have CCR register
+ */
+/**
+ * @brief RTK TIM CCR
+ */
+typedef struct {
+  __IO uint16_t CCRx; /*TIM capture/compare register */
+  __IO uint8_t RSVD;  /*TIM capture/compare rsvd register */
+  __IO uint8_t CCMRx; /*TIM capture/compare register */
+} RTIM_CCR_TypeDef;
+
+/**
+ * RTK Timer (RTIM) registers
+ */
+typedef struct {
+  __IO uint32_t EN;       /* Timer enable */
+  __IO uint32_t CR;       /* Main control settings */
+  __IO uint32_t DIER;     /* DMA/Interrupt configuration */
+  __IO uint32_t SR;       /* Status flags */
+  __IO uint32_t EGR;      /* Event generation control */
+  __IO uint32_t CNT;      /* Counter value */
+  __IO uint32_t PSC;      /* Clock prescaler */
+  __IO uint32_t ARR;      /* Auto-reload value */
+  __IO uint32_t CCMRx[6]; /* Capture/Compare modes */
+} RTIM_TypeDef;
+/** @} */
+
+/* Real-Time Clock (RTC) registers */
+typedef struct {
+  __IO uint32_t TR;     /* Time value */
+  __IO uint32_t CR;     /* Control settings */
+  __IO uint32_t ISR;    /* Status and initialization */
+  __IO uint32_t PRER;   /* Clock prescaler */
+  __IO uint32_t CALIBR; /* Calibration settings */
+  __IO uint32_t ALMR1;  /* Alarm 1 configuration */
+  __IO uint32_t ALMR2;  /* Alarm 2 configuration */
+  __IO uint32_t WPR;    /* Write protection */
+} RTC_TypeDef;
+/** @} */
+
+/* AMEBAZ_PINMUX */
+typedef struct {
+  __IO uint32_t PADCTR[21]; /*Pad control register */
+} PINMUX_TypeDef;
+/** @} */
+
+/* AMEBAZ_IPSEC */
+typedef struct {
+  __IO uint32_t IPSSDAR; /* Source Descriptor Starting Address Register */
+  __IO uint32_t IPSDDAR; /* Destination Descriptor Starting Address Register */
+  __IO uint32_t IPSCSR;  /* Command/Status Register */
+  __IO uint32_t IPSCTR;  /* Control Register */
+} IPSEC_TypeDef;
+/** @} */
+
+/* AMEBAZ_USOC */
+typedef struct {
+  __IO uint32_t SIE_CR;           /* SIE control */
+  __IO uint32_t CLK_RST_CTRL;     /* Clock and reset control */
+  __IO uint32_t CHANN_CTRL;       /* Channel control */
+  __IO uint32_t BUFF_SIZE_CTRL;   /* TX/RX buffer size control */
+  __IO uint32_t TXBD_BAR;         /* TX buffer descriptor base address */
+  __IO uint32_t RXBD_BAR;         /* RX buffer descriptor base address */
+  __IO uint32_t RING_SIZE_CTRL;   /* Ring size control */
+  __IO uint32_t RSVD1;            /* Reserved */
+  __I uint32_t TXBD_HW_IDX;       /* TX hardware index */
+  __IO uint32_t TXBD_SW_IDX;      /* TX software index */
+  __I uint32_t RXBD_HW_IDX;       /* RX hardware index */
+  __IO uint32_t RXBD_SW_IDX;      /* RX software index */
+  __IO uint32_t INTR_MASK;        /* Interrupt mask */
+  __IO uint32_t INTR_CLR;         /* Interrupt clear */
+  __IO uint32_t INTR_STAT;        /* Interrupt status */
+  __IO uint32_t RSVD2;            /* Reserved */
+  __IO uint32_t TX_MIT;           /* TX mitigation */
+  __IO uint32_t RX_MIT;           /* RX mitigation */
+  __IO uint32_t RSVD3[2];         /* Reserved */
+  __IO uint32_t IOREG_MAR;        /* Host device access */
+  __IO uint32_t RSVD4[3];         /* Reserved */
+  __IO uint32_t TX_MAIN_BUF_CTRL; /* TX main buffer control */
+  __IO uint32_t TX_DEST_BUF_CTRL; /* TX destination buffer control */
+  __IO uint32_t RX_MAIN_BUF_CTRL; /* RX main buffer control */
+  __IO uint32_t RX_SRC_BUF_CTRL;  /* RX source buffer control */
+  __IO uint32_t TX_STUCK_TIMER;   /* TX stuck timer */
+  __IO uint32_t RX_STUCK_TIMER;   /* RX stuck timer */
+  __IO uint32_t QOS_CTRL;         /* QoS control */
+} USOC_REG_TypeDef;
+
+/**
+ * NCO32k (Numerically Controlled Oscillator) peripheral structure
+ * Controls and monitors the 32KHz clock generation and calibration system
+ */
+typedef struct {
+  __IO uint32_t CLK_INFO;  // [23:0] Unregulated clock frequency value
+                           // [24] 32K clock output ready flag
+                           // [25] 32K calibration ready flag
+
+  __IO uint32_t CLK_OUT;  // Expected frequency of NCO calibration output clock
+
+  __IO uint32_t CLK_REF;  // Lower 32 bits of reference clock frequency
+                          // Used for clock output generation and input clock
+                          // monitoring (ASIC: OSC8M, FPGA: 128K)
+
+  __IO uint32_t CTRL;  // [9:0] Reference clock frequency (upper 10 bits)
+                       // [16] 32K enable
+                       // [17] Reference clock enable
+                       // [23:20] 32K monitor
+                       // [30:24] 32K threshold
+} NCO32k_TypeDef;
+
+/*
+ * @defgroup AMEBAZ_NCO8M
+ * @{
+ * @brief AMEBAZ_NCO8M Register Declaration
+ * @note [0]: function enable
+ * @note [15:1]: expected frequency of nco output clk, unit is 1KHz
+ * @note [31:16] frequency of nco input clk, unit is 1KHz
+ */
+typedef struct {
+  __IO uint32_t NCOReg;
+} NCO8M_TypeDef;
+/** @} */
+
+/* AMEBAZ_BACKUP_REG */
+typedef struct {
+  __IO uint32_t DWORD[4]; /* 0x138 */
+} BACKUP_REG_TypeDef;
+/** @} */
+
+/* AMEBAZ_CACHE Register Declaration */
+typedef struct {
+  __IO uint32_t SPICC_EN;                /* Enable control */
+  __IO uint32_t SPICC_FLUSH;             /* Cache flush control */
+  __IO uint32_t SPICC_INTR;              /* Interrupt status/control */
+  __IO uint32_t SPICC_RST_CUNT;          /* Reset counter */
+  __IO uint32_t SPICC_RD_EVT_CUNT;       /* Read events counter */
+  __IO uint32_t SPICC_HIT_EVT_CUNT;      /* Cache hit counter */
+  __IO uint32_t SPICC_HIT_LSTW_EVT_CUNT; /* Last-way hit counter */
+  __IO uint32_t SPICC_RD_PEND_CUNT;      /* Pending read counter */
+} SPIC_CACHE_TypeDef;
+/** @} */
+
+/* Control register definitions for system-level configurations */
+typedef struct {
+  /* 0x0000 - Power/Isolation Control */
+  union {
+    struct {
+      __IO uint16_t PWR_CTRL; /* 0x0000 */
+      __IO uint16_t ISO_CTRL; /* 0x0002 */
+    } PWR_ISO;
+    __IO uint32_t PWR_ISO_CTRL; /* 0x0000 */
+  };
+
+  uint32_t RESERVED0[1];   /* 0x0004 */
+  __IO uint32_t FUNC_EN;   /* 0x0008 */
+  __IO uint32_t CLK_CTRL0; /* 0x0010 */
+  __IO uint32_t CLK_CTRL1; /* 0x0014 */
+
+  uint32_t RESERVED1[2]; /* 0x0018-0x001C */
+
+  /* EFUSE System Configuration Registers */
+  __IO uint32_t EFUSE_SYSCFG[8]; /* 0x0020-0x003C */
+
+  __IO uint32_t REGU_CTRL0; /* 0x0040 */
+  uint32_t RESERVED2[1];    /* 0x0044 */
+  __IO uint32_t SWR_CTRL0;  /* 0x0048 */
+  __IO uint32_t SWR_CTRL1;  /* 0x004C */
+
+  uint32_t RESERVED3[4]; /* 0x0050-0x005C */
+
+  /* Crystal Control Registers */
+  __IO uint32_t XTAL_CTRL0; /* 0x0060 */
+  __IO uint32_t XTAL_CTRL1; /* 0x0064 */
+  __IO uint32_t XTAL_CTRL2; /* 0x0068 */
+
+  uint32_t RESERVED4[1]; /* 0x006C */
+
+  /* System PLL Control Registers */
+  __IO uint32_t SYSPLL_CTRL0; /* 0x0070 */
+  __IO uint32_t SYSPLL_CTRL1; /* 0x0074 */
+  __IO uint32_t SYSPLL_CTRL2; /* 0x0078 */
+  __IO uint32_t SYSPLL_CTRL3; /* 0x007C */
+
+  uint32_t RESERVED5[4]; /* 0x0080-0x008C */
+
+  __IO uint32_t ANA_TIM_CTRL;      /* 0x0090 */
+  __IO uint32_t DSLP_TIM_CTRL;     /* 0x0094 */
+  __IO uint32_t DSLP_TIM_CAL_CTRL; /* 0x0098 */
+
+  uint32_t RESERVED6[2]; /* 0x009C-0x00A0 */
+
+  __IO uint32_t DEBUG_CTRL;            /* 0x00A0 */
+  __IO uint32_t PINMUX_CTRL;           /* 0x00A4 */
+  __IO uint32_t GPIO_DSTBY_WAKE_CTRL0; /* 0x00A8 */
+  __IO uint32_t GPIO_DSTBY_WAKE_CTRL1; /* 0x00AC */
+
+  uint32_t RESERVED7[3]; /* 0x00B0-0x00B8 */
+
+  __IO uint32_t DEBUG_REG; /* 0x00BC */
+
+  uint32_t RESERVED8[8]; /* 0x00C0-0x00DC */
+
+  __IO uint32_t EEPROM_CTRL0;           /* 0x00E0 */
+  __IO uint32_t EEPROM_CTRL1;           /* 0x00E4 */
+  __IO uint32_t EFUSE_CTRL;             /* 0x00E8 */
+  __IO uint32_t EFUSE_TEST;             /* 0x00EC */
+  __IO uint32_t OSC32K_CTRL;            /* 0x00F0 */
+  __IO uint32_t OSC32K_RCAL;            /* 0x00F4 */
+  __IO uint32_t DSTBY_INFO0;            /* 0x00F8 */
+  __IO uint32_t DSTBY_INFO1;            /* 0x00FC */
+  __IO uint32_t SLP_WAKE_EVENT_MSK0;    /* 0x0100 */
+  __IO uint32_t SLP_WAKE_EVENT_MSK1;    /* 0x0104 */
+  __IO uint32_t SLP_WAKE_EVENT_STATUS0; /* 0x0108 */
+  __IO uint32_t SLP_WAKE_EVENT_STATUS1; /* 0x010C */
+  __IO uint32_t SNF_WAKE_EVENT_MSK0;    /* 0x0110 */
+  __IO uint32_t SNF_WAKE_EVENT_STATUS;  /* 0x0114 */
+  __IO uint32_t PWRMGT_CTRL;            /* 0x0118 */
+
+  uint32_t RESERVED9[1]; /* 0x011C */
+
+  __IO uint32_t PWRMGT_OPTION;     /* 0x0120 */
+  __IO uint32_t PWRMGT_OPTION_EXT; /* 0x0124 */
+
+  uint32_t RESERVED10[2]; /* 0x0128-0x012C */
+
+  __IO uint32_t DSLP_WEVENT;  /* 0x0130 */
+  __IO uint32_t PERI_MONITOR; /* 0x0134 */
+  __IO uint32_t NORESET_FF;   /* 0x0138 */
+
+  uint32_t RESERVED11[45]; /* 0x013C-0x01EC */
+
+  __IO uint32_t SYSTEM_CFG0; /* 0x01F0 */
+  __IO uint32_t SYSTEM_CFG1; /* 0x01F4 */
+  __IO uint32_t SYSTEM_CFG2; /* 0x01F8 */
+} SYSTEM_CTRL_TypeDef;
+
+/* Peripheral and clock control register definitions */
+typedef struct {
+  __IO uint32_t PEON_PWR_CTRL;         /* 0x0200 */
+  __IO uint32_t PON_ISO_CTRL;          /* 0x0204 */
+  uint32_t RESERVED0[2];               /* 0x0208-0x020C */
+  __IO uint32_t SOC_FUNC_EN;           /* 0x0210 */
+  __IO uint32_t SOC_HCI_COM_FUNC_EN;   /* 0x0214 */
+  __IO uint32_t SOC_PERI_FUNC0_EN;     /* 0x0218 */
+  __IO uint32_t SOC_PERI_FUNC1_EN;     /* 0x021C */
+  __IO uint32_t SOC_PERI_BD_FUNC0_EN;  /* 0x0220 */
+  uint32_t RESERVED1[3];               /* 0x0224-0x022C */
+  __IO uint32_t PESOC_CLK_CTRL;        /* 0x0230 */
+  __IO uint32_t PESOC_PERI_CLK_CTRL0;  /* 0x0234 */
+  __IO uint32_t PESOC_PERI_CLK_CTRL1;  /* 0x0238 */
+  __IO uint32_t PESOC_CLK_CTRL3;       /* 0x023C */
+  __IO uint32_t PESOC_HCI_CLK_CTRL0;   /* 0x0240 */
+  __IO uint32_t PESOC_COM_CLK_CTRL1;   /* 0x0244 */
+  __IO uint32_t PESOC_HW_ENG_CLK_CTRL; /* 0x0248 */
+  uint32_t RESERVED2[1];               /* 0x024C */
+  __IO uint32_t PESOC_CLK_SEL;         /* 0x0250 */
+  uint32_t RESERVED3[6];               /* 0x0254-0x0268 */
+  __IO uint32_t UART_NCO_CTRL;         /* 0x026C */
+  uint32_t RESERVED4[1];               /* 0x0270 */
+  __IO uint32_t OSC32K_REG_CTRL0;      /* 0x0274 */
+  __IO uint32_t OSC32K_REG_CTRL1;      /* 0x0278 */
+  __IO uint32_t THERMAL_METER_CTRL;    /* 0x027C */
+  __IO uint32_t GPIO_PINMUX_CTRL[24];  /* 0x0280-0x02DC */
+  __IO uint32_t PON_PINMUX_CTRL;       /* 0x02E0 */
+  uint32_t RESERVED5[6];               /* 0x02E4-0x02F8 */
+  __IO uint32_t FW_PPROTECT_KEY_CTRL;  /* 0x02FC */
+  uint32_t RESERVED6[1];               /* 0x0300 */
+  __IO uint32_t PESOC_SOC_CTRL;        /* 0x0304 */
+} PERI_ON_TypeDef;
+
+/* GPIO (General Purpose Input/Output) register definitions */
+typedef struct {
+  __IO uint32_t DR;   /* Data Register */
+  __IO uint32_t DDR;  /* Direction Register */
+  __IO uint32_t CTRL; /* Control Register */
+} GPIO_Port_TypeDef;
+
+typedef struct {
+  GPIO_Port_TypeDef PORT[4];  /*GPIO IP have 4 ports */
+  __IO uint32_t INT_EN;       /* GPIO interrupt enable register */
+  __IO uint32_t INT_MASK;     /* GPIO interrupt mask register */
+  __IO uint32_t INT_TYPE;     /* interrupt type(level/edge) register */
+  __IO uint32_t INT_POLARITY; /* interrupt polarity(Active low/high) register */
+  __IO uint32_t INT_STATUS;   /* interrupt status register */
+  __IO uint32_t INT_RAWSTATUS; /* interrupt status without mask register */
+  __IO uint32_t DEBOUNCE;      /* interrupt signal debounce register */
+  __IO uint32_t PORTA_EOI;     /* clear interrupt register */
+  __IO uint32_t EXT_PORT[4];   /* GPIO IN read or OUT read back register */
+  __IO uint32_t LSSYNC;    /* level-sensitive synchronization enable register */
+  __IO uint32_t IDCODE;    /* GPIO ID code register */
+  __IO uint32_t RSVD2;     /* Reserved */
+  __IO uint32_t VERIDCODE; /* component Version register */
+  __IO uint32_t CONFIG2;   /* GPIO configuration Register 2 */
+  __IO uint32_t CONFIG1;   /* GPIO configuration Register 1 */
+} GPIO_TypeDef;
+
+/* Peripheral memory map */
+#define SYSTEM_CTRL_BASE 0x40000000
+#define PERI_ON_BASE (SYSTEM_CTRL_BASE + 0x200)
+
+#define VENDOR_REG_BASE 0x40002800
+#define SPI_FLASH_BASE 0x08000000
+
+#define NCO1_REG_BASE 0x40000080
+#define BACKUP_REG_BASE 0x40000138
+#define NCO2_REG_BASE 0x4000026C
+#define PINMUX_REG_BASE 0x40000280
+
+#define GPIO_REG_BASE 0x40001000
+#define TIMER_REG_BASE 0x40002000
+#define LOG_UART_REG_BASE 0x40003000
+#define RTC_BASE 0x40003400
+#define SPIC_CACHE_BASE 0x40003C00
+#define ADC_REG_BASE 0x40010000
+#define SPI_FLASH_CTRL_BASE 0x40020000
+#define UART0_REG_BASE 0x40040000
+#define UART1_REG_BASE 0x40040400
+#define UART2_REG_BASE LOG_UART_REG_BASE
+#define SPI0_REG_BASE 0x40042000
+#define SPI1_REG_BASE 0x40042400
+#define I2C0_REG_BASE 0x40044000
+#define I2C1_REG_BASE 0x40044400
+#define SDIO_DEVICE_REG_BASE 0x40050000
+#define GDMA0_REG_BASE 0x40060000
+#define GDMA1_REG_BASE 0x40061000
+#define I2S0_REG_BASE 0x40062000
+#define CRYPTO_REG_BASE 0x40070000
+#define WIFI_REG_BASE 0x40080000
+#define SIE_REG_BASE 0x400C0000
+#define USOC_REG_BASE 0x400C2000
+#define GDMA1_REG_OFF 0x1000
+
+#define TIM0_BASE (TIMER_REG_BASE)
+#define TIM1_BASE (TIMER_REG_BASE + 0x040)
+#define TIM2_BASE (TIMER_REG_BASE + 0x080)
+#define TIM3_BASE (TIMER_REG_BASE + 0x0C0)
+#define TIM4_BASE (TIMER_REG_BASE + 0x100)
+#define TIM5_BASE (TIMER_REG_BASE + 0x140)
+
+/* Peripheral declaration */
+#define SYSTEM_CTRL ((SYSTEM_CTRL_TypeDef *)SYSTEM_CTRL_BASE)
+#define PERI_ON ((PERI_ON_TypeDef *)PERI_ON_BASE)
+
+#define UART0 ((UART_TypeDef *)UART0_REG_BASE)
+#define UART1 ((UART_TypeDef *)UART1_REG_BASE)
+#define UART2 ((UART_TypeDef *)LOG_UART_REG_BASE)
+#define SPI0 ((SPI_TypeDef *)SPI0_REG_BASE)
+#define SPI1 ((SPI_TypeDef *)SPI1_REG_BASE)
+#define SPIC ((SPIC_TypeDef *)SPI_FLASH_CTRL_BASE)
+#define ADC ((ADC_TypeDef *)ADC_REG_BASE)
+#define I2C0 ((I2C_TypeDef *)I2C0_REG_BASE)
+#define I2C1 ((I2C_TypeDef *)I2C1_REG_BASE)
+#define I2S ((I2S_TypeDef *)I2S0_REG_BASE)
+#define TIM0 ((RTIM_TypeDef *)TIM0_BASE)
+#define TIM1 ((RTIM_TypeDef *)TIM1_BASE)
+#define TIM2 ((RTIM_TypeDef *)TIM2_BASE)
+#define TIM3 ((RTIM_TypeDef *)TIM3_BASE)
+#define TIM4 ((RTIM_TypeDef *)TIM4_BASE)
+#define TIM5 ((RTIM_TypeDef *)TIM5_BASE)
+#define RTC ((RTC_TypeDef *)RTC_BASE)
+#define PINMUX ((PINMUX_TypeDef *)PINMUX_REG_BASE)
+#define IPSEC ((IPSEC_TypeDef *)CRYPTO_REG_BASE)
+#define USOC_REG ((USOC_REG_TypeDef *)USOC_REG_BASE)
+#define NCO32k ((NCO32k_TypeDef *)NCO1_REG_BASE)
+#define NCO8M ((NCO8M_TypeDef *)NCO2_REG_BASE)
+#define BACKUP_REG ((BACKUP_REG_TypeDef *)BACKUP_REG_BASE)
+#define SPIC_CACHE ((SPIC_CACHE_TypeDef *)SPIC_CACHE_BASE)
+
+#define GPIOA ((GPIO_Port_TypeDef *)(GPIO_REG_BASE + 0x00))
+#define GPIOB ((GPIO_Port_TypeDef *)(GPIO_REG_BASE + 0x0C))
+#define GPIOC ((GPIO_Port_TypeDef *)(GPIO_REG_BASE + 0x18))
+
+#define GPIO_COMMON ((GPIO_Common_TypeDef *)(GPIO_REG_BASE + 0x30))
+
+/* rtl8711b_peri_on.h */
+// 2 0x200 REG_PEON_PWR_CTRL
+#define BIT_SOC_UAHV_EN (1 << 2)
+#define BIT_SOC_UALV_EN (1 << 1)
+#define BIT_SOC_USBD_EN (1 << 0)
+
+// 2 0x210 REG_SOC_FUNC_EN
+#define BIT_SOC_BOOT_FROM_JTAG (1 << 31)
+#define BIT_SOC_UNLOCK_FROM_JTAG (1 << 30)
+#define BIT_SOC_WAKE_FROM_PS (1 << 29)
+#define BIT_SOC_PATCH_FUNC0 (1 << 28)
+#define BIT_SOC_PATCH_FUNC1 (1 << 27)
+#define BIT_SOC_PATCH_FUNC2 (1 << 26)
+
+#define BIT_SOC_XMODEM_PAGE_PG (1 << 25)
+#define BIT_SOC_XMODEM_FLASH_EMPTY (1 << 24)
+
+#define BIT_SOC_SECURITY_ENGINE_EN (1 << 20)
+#define BIT_SOC_GTIMER_EN (1 << 16)
+#define BIT_SOC_GDMA1_EN (1 << 14)
+#define BIT_SOC_GDMA0_EN (1 << 13)
+#define BIT_SOC_LOG_UART_EN (1 << 12)
+#define BIT_SOC_CPU_EN (1 << 8)
+#define BIT_SOC_MEM_CTRL_EN (1 << 6)
+#define BIT_SOC_FLASH_EN (1 << 4)
+#define BIT_SOC_LXBUS_EN (1 << 2)
+#define BIT_SOC_OCP_EN (1 << 1)
+#define BIT_SOC_FUN_EN (1 << 0)
+
+// 2 0x0214 REG_SOC_HCI_COM_FUNC_EN
+#define BIT_SOC_HCI_WL_MACON_EN (1 << 16)
+#define BIT_SOC_HCI_SM_SEL (1 << 13)
+#define BIT_SOC_HCI_OTG_RST_MUX (1 << 5)
+#define BIT_SOC_HCI_OTG_EN (1 << 4)
+#define BIT_SOC_HCI_SDIOD_ON_RST_MUX (1 << 3)
+#define BIT_SOC_HCI_SDIOD_OFF_EN (1 << 1)
+#define BIT_SOC_HCI_SDIOD_ON_EN (1 << 0)
+
+// 2 0x0218 REG_SOC_PERI_FUNC0_EN
+#define BIT_PERI_I2S0_EN (1 << 24)
+#define BIT_PERI_I2C1_EN (1 << 17)
+#define BIT_PERI_I2C0_EN (1 << 16)
+#define BIT_PERI_SPI1_EN (1 << 9)
+#define BIT_PERI_SPI0_EN (1 << 8)
+#define BIT_PERI_UART2_EN (1 << 2)
+#define BIT_PERI_UART1_EN (1 << 1)
+#define BIT_PERI_UART0_EN (1 << 0)
+
+// 2 0x021C REG_SOC_PERI_FUNC1_EN
+#define BIT_PERI_GPIO_EN (1 << 8)
+#define BIT_PERI_ADC0_EN (1 << 0)
+
+// 2 0x0220 REG_SOC_PERI_BD_FUNC0_EN
+#define BIT_PERI_UART2_BD_EN (1 << 2)
+#define BIT_PERI_UART1_BD_EN (1 << 1)
+#define BIT_PERI_UART0_BD_EN (1 << 0)
+
+// 2 0x0230 REG_PESOC_CLK_CTRL
+#define BIT_SOC_SLPCK_BTCMD_EN (1 << 29)
+#define BIT_SOC_ACTCK_BTCMD_EN (1 << 28)
+#define BIT_SOC_ACTCK_GPIO_EN (1 << 24)
+#define BIT_SOC_ACTCK_GDMA1_EN (1 << 18)
+#define BIT_SOC_ACTCK_GDMA0_EN (1 << 16)
+#define BIT_SOC_ACTCK_TIMER_EN (1 << 14)
+#define BIT_SOC_ACTCK_LOG_UART_EN (1 << 12)
+#define BIT_SOC_ACTCK_FLASH_EN (1 << 8)
+#define BIT_SOC_ACTCK_VENDOR_REG_EN (1 << 6)
+#define BIT_SOC_ACTCK_TRACE_EN (1 << 4)
+#define BIT_SOC_CKE_PLFM (1 << 2)
+#define BIT_SOC_CKE_OCP (1 << 0)
+
+// 2 0x0234 REG_PESOC_PERI_CLK_CTRL0
+#define BIT_SOC_ACTCK_SPI1_EN (1 << 18)
+#define BIT_SOC_ACTCK_SPI0_EN (1 << 16)
+#define BIT_SOC_ACTCK_UART1_EN (1 << 2)
+#define BIT_SOC_ACTCK_UART0_EN (1 << 0)
+
+// 2 0x0238 REG_PESOC_PERI_CLK_CTRL1
+#define BIT_SOC_ACTCK_ADC_EN (1 << 24)
+#define BIT_SOC_ACTCK_I2S_EN (1 << 16)
+#define BIT_SOC_ACTCK_I2C1_EN (1 << 2)
+#define BIT_SOC_ACTCK_I2C0_EN (1 << 0)
+
+// 2 0x0240 REG_PESOC_HCI_CLK_CTRL0
+#define BIT_SOC_ACTCK_OTG_EN (1 << 4)
+#define BIT_SOC_ACTCK_SDIO_HST_EN \
+  (1 << 2)  // SDIO_HST clock enable in CPU run mode
+#define BIT_SOC_ACTCK_SDIO_DEV_EN \
+  (1 << 0)  // SDIO_DEV clock enable in CPU run mode
+
+/* REG_PESOC_CLK_SEL 0x0250 */
+#define BIT_SHIFT_PESOC_UART1_SCLK_SEL 26
+/* [27:26] uart1 rx clock, 01: osc 8m;   00: xtal;    10: xtal nco */
+#define BIT_MASK_PESOC_UART1_SCLK_SEL 0x03
+#define BIT_SHIFT_PESOC_UART0_SCLK_SEL 19
+/* [20:19] uart0 rx clock, 01: osc 8m;   00: xtal;    10: xtal nco */
+#define BIT_MASK_PESOC_UART0_SCLK_SEL 0x03
+
+/* 1: enable to generate flash clock (with phase shift) divided by 500M pll
+ * clock, HW detect this signal's rising edge to start the phase shift clock
+ * division circuit. */
+#define BIT_FLASH_CK_PS_DIV_EN (1 << 25)
+/* 1: enable to generate flash clock (no phase shift) divided by 500M pll clock,
+ * HW detect this signal's rising edge to start the no phase shift division
+ * circuit. */
+#define BIT_FLASH_CK_DIV_EN (1 << 24)
+/* 1: delay flash sout for calibration;  0: bypass flash sout to spic */
+#define BIT_FLASH_CAL_EN (1 << 23)
+#define BIT_SHIFT_FLASH_CK_PS_INT 12
+/* [14:12] Flash clock phase shift in units of 500M pll clock cycels */
+#define BIT_MASK_FLASH_CK_PS_INT 0x03
+/* ready flag of Flash clock with phase shift, Read only */
+#define BIT_FLASH_PS_DIV_RDY (1 << 7)
+/* ready flag of Flash clock, Read only */
+#define BIT_FLASH_DIV_RDY (1 << 6)
+#define BIT_SHIFT_PESOC_TRACE_CK_SEL 4
+/* [5:4] "Trace clock select0: 12.5MH1: 25MHz2: 50MHz3: 100MHz" */
+#define BIT_MASK_PESOC_TRACE_CK_SEL 0x03
+/* "Only valid when r_FLASH_DIV_FRAC= 1, it decides the duty cycle of flash
+ * clock when not divided by integer1: duty cycle > 50% ; 0: duty cycle < 50%"
+ */
+#define BIT_FLASH_DIV_HIGH_FRAC (1 << 3)
+/* "Flash clock division ratio, fractional part0: no fraction, only divided by
+ * integer set by bit[1:0],  1: 0.5" */
+#define BIT_FLASH_DIV_FRAC (1 << 2)
+#define BIT_SHIFT_DIV_INT 0
+/* [1:0] "Flash clock division ratio, integrate part0: divided by 21: divided by
+ * 32: divided by 43: divided by 5" */
+#define BIT_MASK_FLASH_DIV_INT 0x03
+
+// 0x0244 REG_PESOC_COM_CLK_CTRL1
+#define BIT_SOC_ACTCK_SECURITY_ENG_EN (1 << 4)
+// spec name is wrong (BIT_SOC_ACTCK_WL_EN)
+#define BIT_SOC_ACTCK_LXBUS_EN (1 << 0)
+
+// 0x02E0 REG_PON_PINMUX_CTRL
+#define BIT_HCI_SDIOD_PIN_EN (1 << 0)
+
+// 0x0304 REG_PESOC_SOC_CTRL
+#define BIT_PESOC_LX_SLV_SWAP_SEL (1 << 10)
+#define BIT_PESOC_LX_MST_SWAP_SEL (1 << 9)
+#define BIT_PESOC_LX_WL_SWAP_SEL (1 << 8)
+
+// 0x2FC REG_FW_PPROTECT_KEY_CTRL
+#define BIT_RDP_EN (1 << 3) /* load from efuse */
+#define BIT_RDP_EN_LOAD (1 << 2)
+#define BIT_RDP_KEY_REQ (1 << 1)
+#define BIT_OTF_KEY_REQ (1 << 0)
+
+/* rtl8711b_pinmux.h */
+#define _PA_0 (0x00)
+#define _PA_1 (0x01)
+#define _PA_2 (0x02)
+#define _PA_3 (0x03)
+#define _PA_4 (0x04)
+#define _PA_5 (0x05)
+#define _PA_6 (0x06)
+#define _PA_7 (0x07)
+#define _PA_8 (0x08)
+#define _PA_9 (0x09)
+#define _PA_10 (0x0A)
+#define _PA_11 (0x0B)
+#define _PA_12 (0x0C)
+#define _PA_13 (0x0D)
+#define _PA_14 (0x0E)
+#define _PA_15 (0x0F)
+#define _PA_16 (0x10)
+#define _PA_17 (0x11)
+#define _PA_18 (0x12)
+#define _PA_19 (0x13)
+#define _PA_20 (0x14)
+#define _PA_21 (0x15)
+#define _PA_22 (0x16)
+#define _PA_23 (0x17)
+#define _PA_24 (0x18)
+#define _PA_25 (0x19)
+#define _PA_26 (0x1A)
+#define _PA_27 (0x1B)
+#define _PA_28 (0x1C)
+#define _PA_29 (0x1D)
+#define _PA_30 (0x1E)
+#define _PA_31 (0x1F)
+#define _PB_0 (0x20)
+#define _PB_1 (0x21)
+#define _PB_2 (0x22)
+#define _PB_3 (0x23)
+#define _PB_4 (0x24)
+#define _PB_5 (0x25)
+#define _PB_6 (0x26)
+#define _PB_7 (0x27)
+#define _PB_8 (0x28)
+#define _PNC (0xFFFFFFFF)
+
+// PINMUX function modes
+#define PINMUX_FN_GPIO 0x100      // Normal GPIO mode
+#define PINMUX_FN_UART 0x101      // UART function
+#define PINMUX_FN_SPIM 0x102      // SPI1 function (why diff function code?)
+#define PINMUX_FN_SPIS 0x103      // SPI0 function
+#define PINMUX_FN_SPIF 0x104      // SPI Flash interface
+#define PINMUX_FN_I2C 0x105       // I2C function
+#define PINMUX_FN_SDIO 0x106      // SDIO function
+#define PINMUX_FN_PWM 0x107       // PWM
+#define PINMUX_FN_TIMINPUT 0x107  // PWM
+#define PINMUX_FN_SWD 0x108
+#define PINMUX_FN_EXT32K 0x108
+#define PINMUX_FN_RTCOUT 0x108
+#define PINMUX_FN_SWD 0x108  // SWD/JTAG function
+#define PINMUX_FN_I2S 0x109  // I2S function
+#define PINMUX_FN_COEX_EXT32K 0x10a
+#define PINMUX_FN_BTCOEX 0x10a
+#define PINMUX_FN_WLLED 0x10a
+
+#define PAD_DRV_STRENGTH_0 (0x00000000 << 9)
+#define PAD_DRV_STRENGTH_1 (0x00000001 << 9)
+#define PAD_DRV_STRENGTH_2 (0x00000002 << 9)
+#define PAD_DRV_STRENGTH_3 (0x00000003 << 9)
+#define PAD_DRV_STRENGTH_4 (0x00000004 << 9)
+#define PAD_DRV_STRENGTH_5 (0x00000005 << 9)
+#define PAD_DRV_STRENGTH_6 (0x00000006 << 9)
+#define PAD_DRV_STRENGTH_7 (0x00000007 << 9)
+
+static inline void PINMUX_Config_BL(uint32_t pin, uint32_t func) {
+  volatile uint32_t *reg = &PERI_ON->GPIO_PINMUX_CTRL[pin >> 1];
+  uint32_t shift = (pin & 1) << 4;
+  uint32_t mask = 0xFFFF << shift;
+  *reg = (*reg & ~mask) | (func << shift);
+}
+
+static inline void PINMUX_Config(uint32_t pin, uint32_t func) {
+  volatile uint32_t *reg = &PERI_ON->GPIO_PINMUX_CTRL[pin >> 1];
+  if (pin & 1) {
+    *reg = (*reg & 0x0000FFFF) | (func << 16);
+  } else {
+    *reg = (*reg & 0xFFFF0000) | func;
+  }
+}
+
+static inline void PINMUX_ConfigPadPull(uint8_t pin, uint8_t pull_type) {
+  uint32_t reg_index = pin >> 1;
+  uint32_t bit_pos = (pin & 1) << 4;
+  uint32_t mask = 0xC0U << bit_pos;
+
+  PINMUX->PADCTR[reg_index] =
+      (PINMUX->PADCTR[reg_index] & ~mask) | (pull_type << bit_pos);
+}
+
+/* rtl8711b_gpio.h */
+
+/* GPIO_Pull_parameter_definitions */
+#define GPIO_PuPd_NOPULL 0x00    // 00
+#define GPIO_PuPd_SHUTDOWN 0x00  // 00
+#define GPIO_PuPd_DOWN 0x80      // 10
+#define GPIO_PuPd_UP 0x40        // 01
+
+/* GPIO_INT_Trigger_parameter_definitions  */
+#define GPIO_INT_Trigger_LEVEL 0x0 /*This interrupt is level trigger  */
+#define GPIO_INT_Trigger_EDGE 0x1  /*This interrupt is edge trigger  */
+
+#define IS_GPIOIT_LEVEL_TYPE(TYPE) \
+  (((TYPE) == GPIO_INT_Trigger_LEVEL) || ((TYPE) == GPIO_INT_Trigger_EDGE))
+
+/* GPIO_INT_Polarity_parameter_definitions */
+/*Setting interrupt to low active: falling edge or low level  */
+#define GPIO_INT_POLARITY_ACTIVE_LOW 0x0
+/*Setting interrupt to high active: rising edge or high level */
+#define GPIO_INT_POLARITY_ACTIVE_HIGH 0x1
+
+#define IS_GPIOIT_POLARITY_TYPE(TYPE)          \
+  (((TYPE) == GPIO_INT_POLARITY_ACTIVE_LOW) || \
+   ((TYPE) == GPIO_INT_POLARITY_ACTIVE_HIGH))
+
+/* GPIO_INT_Debounce_parameter_definitions */
+#define GPIO_INT_DEBOUNCE_DISABLE 0x0 /*Disable interrupt debounce */
+#define GPIO_INT_DEBOUNCE_ENABLE 0x1  /*Enable interrupt debounce */
+
+#define IS_GPIOIT_DEBOUNCE_TYPE(TYPE)       \
+  (((TYPE) == GPIO_INT_DEBOUNCE_DISABLE) || \
+   ((TYPE) == GPIO_INT_DEBOUNCE_ENABLE))
+
+/* rtl8711b_rcc.h */
+
+/* 0x230 REG_PESOC_CLK_CTRL */
+#define APBPeriph_GPIO_CLOCK (BIT_SOC_ACTCK_GPIO_EN)
+#define APBPeriph_GDMA1_CLOCK (BIT_SOC_ACTCK_GDMA1_EN)
+#define APBPeriph_GDMA0_CLOCK (BIT_SOC_ACTCK_GDMA0_EN)
+#define APBPeriph_GTIMER_CLOCK (BIT_SOC_ACTCK_TIMER_EN)
+#define APBPeriph_LOGUART_CLOCK (BIT_SOC_ACTCK_LOG_UART_EN)
+#define APBPeriph_FLASH_CLOCK (BIT_SOC_ACTCK_FLASH_EN)
+#define APBPeriph_VENDOR_REG_CLOCK (BIT_SOC_ACTCK_VENDOR_REG_EN)
+#define APBPeriph_TRACE_CLOCK (BIT_SOC_ACTCK_TRACE_EN)
+
+/* 0x210 REG_SOC_FUNC_EN */
+#define APBPeriph_SECURITY_ENGINE BIT_SOC_SECURITY_ENGINE_EN
+#define APBPeriph_GTIMER BIT_SOC_GTIMER_EN
+#define APBPeriph_GDMA1 BIT_SOC_GDMA1_EN
+#define APBPeriph_GDMA0 BIT_SOC_GDMA0_EN
+#define APBPeriph_FLASH BIT_SOC_FLASH_EN
+#define APBPeriph_LXBUS BIT_SOC_LXBUS_EN
+
+#endif