chore: blinky
This commit is contained in:
985
include/rtl8710bx.h
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985
include/rtl8710bx.h
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@@ -0,0 +1,985 @@
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#ifndef RTL8710BX_H
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#define RTL8710BX_H
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typedef enum IRQn {
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Reset_IRQn = -15, /* Reset Vector, invoked on Power up and warm reset */
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NonMaskableInt_IRQn =
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-14, /* Non maskable Interrupt, cannot be stopped or preempted */
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HardFault_IRQn = -13, /* Hard Fault, all classes of Fault */
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MemoryManagement_IRQn = -12, /* Memory Management, MPU mismatch, including
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Access Violation and No Match */
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BusFault_IRQn = -11, /* Bus Fault, Pre-Fetch-, Memory Access, other
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address/memory Fault */
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UsageFault_IRQn =
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-10, /* Usage Fault, i.e. Undef Instruction, Illegal State Transition */
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SecureFault_IRQn = -9, /* Secure Fault Interrupt */
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SVCall_IRQn = -5, /* System Service Call via SVC instruction */
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DebugMonitor_IRQn = -4, /* Debug Monitor */
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PendSV_IRQn = -2, /* Pendable request for system service */
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SysTick_IRQn = -1, /* System Tick Timer */
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/* RTL8710BX specific interrupts */
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PWR_Wakeup_IRQn = 0, /* System wakeup from power save interrupt */
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WDG_IRQn = 1, /* Window watchdog interrupt */
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TIM0_IRQn = 2, /* Timer 0 global interrupt */
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TIM1_IRQn = 3, /* Timer 1 global interrupt */
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TIM2_IRQn = 4, /* Timer 2 global interrupt */
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TIM3_IRQn = 5, /* Timer 3 global interrupt */
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SPI0_IRQn = 6, /* SPI0 global interrupt */
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GPIO_IRQn = 7, /* GPIO global interrupt */
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UART0_IRQn = 8, /* UART0 global interrupt */
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FLASH_IRQn = 9, /* Flash memory global interrupt */
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UART1_IRQn = 10, /* UART1 global interrupt */
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TIM4_IRQn = 11, /* Timer 4 global interrupt */
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SDIO_IRQn = 12, /* SDIO global interrupt */
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I2S0_PCM0_IRQn = 13, /* I2S0/PCM0 global interrupt */
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TIM5_IRQn = 14, /* Timer 5 global interrupt */
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WLAN_DMA_IRQn = 15, /* WLAN DMA global interrupt */
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WLAN_Protocol_IRQn = 16, /* WLAN protocol global interrupt */
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Crypto_IRQn = 17, /* Cryptography global interrupt */
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SPI1_IRQn = 18, /* SPI1 global interrupt */
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Periph_IRQn = 19, /* Peripheral global interrupt */
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DMA0_Channel0_IRQn = 20, /* DMA0 Channel 0 global interrupt */
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DMA0_Channel1_IRQn = 21, /* DMA0 Channel 1 global interrupt */
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DMA0_Channel2_IRQn = 22, /* DMA0 Channel 2 global interrupt */
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DMA0_Channel3_IRQn = 23, /* DMA0 Channel 3 global interrupt */
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DMA0_Channel4_IRQn = 24, /* DMA0 Channel 4 global interrupt */
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DMA0_Channel5_IRQn = 25, /* DMA0 Channel 5 global interrupt */
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I2C0_IRQn = 26, /* I2C0 global interrupt */
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I2C1_IRQn = 27, /* I2C1 global interrupt */
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UART_Log_IRQn = 28, /* Log UART global interrupt */
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ADC_IRQn = 29, /* ADC global interrupt */
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RDP_IRQn = 30, /* CPU RDP protection interrupt */
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RTC_IRQn = 31, /* RTC global interrupt */
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DMA1_Channel0_IRQn = 32, /* DMA1 Channel 0 global interrupt */
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DMA1_Channel1_IRQn = 33, /* DMA1 Channel 1 global interrupt */
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DMA1_Channel2_IRQn = 34, /* DMA1 Channel 2 global interrupt */
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DMA1_Channel3_IRQn = 35, /* DMA1 Channel 3 global interrupt */
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DMA1_Channel4_IRQn = 36, /* DMA1 Channel 4 global interrupt */
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DMA1_Channel5_IRQn = 37, /* DMA1 Channel 5 global interrupt */
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USB_IRQn = 38, /* USB global interrupt */
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RXI300_IRQn = 39, /* RXI300 global interrupt */
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USB_SIE_IRQn = 40, /* USB SIE global interrupt */
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} IRQn_Type;
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#define __CM4_REV 0x0101 /* Core Revision r0p1 */
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#define __Vendor_SysTickConfig 0U /* Standard ARM SysTick implementation */
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#define __NVIC_PRIO_BITS 4U /* Cortex-M4 uses 4 bits for priority levels */
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#define __VTOR_PRESENT 1U /* Vector Table Offset Register is present */
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#define __MPU_PRESENT 1U /* Memory Protection Unit is present */
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#define __FPU_PRESENT 1U /* Floating Point Unit is present on this M4 */
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#define __FPU_DP 0U /* Single-precision FPU */
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#define __DSP_PRESENT 1U /* DSP extensions are present on M4 */
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#define __SAUREGION_PRESENT 0U /* No Security Attribution Unit */
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#define __PMU_PRESENT 0U /* No Performance Monitoring Unit */
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#define __PMU_NUM_EVENTCNT 0U /* Not applicable since no PMU */
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#define __ICACHE_PRESENT 0U /* No instruction cache */
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#define __DCACHE_PRESENT 0U /* No data cache */
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#define __DTCM_PRESENT 0U /* No DTCM */
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#include "cmsis/core_cm4.h"
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/* Device Specific Peripheral Section */
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/* AMEBAZ_UART */
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typedef struct {
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__IO uint32_t DLL; /* Divisor Latch (unused in Amebaz) */
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__IO uint32_t DLH_INTCR; /* Interrupt Enable */
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__IO uint32_t INTID; /* Interrupt Identification */
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__IO uint32_t LCR; /* Line Control */
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__IO uint32_t MCR; /* Modem Control */
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__I uint32_t LSR; /* Line Status */
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__I uint32_t MDSR; /* Modem Status */
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__IO uint32_t SPR; /* Scratch Pad */
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__IO uint32_t STSR; /* STS Register */
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__IO uint32_t RB_THR; /* Receive Buffer/Transmit Holding */
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__IO uint32_t MISCR; /* Misc Control */
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__IO uint32_t TXPLSR; /* IrDA TX Pulse Width Control */
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__IO uint32_t RXPLSR; /* IrDA RX Pulse Width Control */
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__IO uint32_t BAUDMONR; /* Baud Monitor */
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__IO uint32_t RSVD2; /* Reserved */
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__IO uint32_t DBG_UART; /* Debug */
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/* Power save features */
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__IO uint32_t RX_PATH; /* RX Path Control */
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__IO uint32_t MON_BAUD_CTRL; /* Monitor Baud Rate Control */
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__IO uint32_t MON_BAUD_STS; /* Monitor Baud Rate Status */
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__IO uint32_t MON_CYC_NUM; /* Monitor Cycle Number */
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__IO uint32_t RX_BYTE_CNT; /* RX Byte Counter */
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__IO uint32_t FCR; /* FIFO Control */
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} UART_TypeDef;
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/** @} */
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/* AMEBAZ_SPI */
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typedef struct {
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__IO uint32_t CTRLR0; /* Control register 0 */
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__IO uint32_t CTRLR1; /* Control register 1 */
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__IO uint32_t SSIENR; /* SSI enable */
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__IO uint32_t MWCR; /* Microwire control */
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__IO uint32_t SER; /* Slave enable */
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__IO uint32_t BAUDR; /* Baud rate select */
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__IO uint32_t TXFTLR; /* TX FIFO threshold level */
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__IO uint32_t RXFTLR; /* RX FIFO threshold level */
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__I uint32_t TXFLR; /* TX FIFO level */
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__I uint32_t RXFLR; /* RX FIFO level */
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__I uint32_t SR; /* Status */
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__IO uint32_t IMR; /* Interrupt mask */
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__I uint32_t ISR; /* Interrupt status */
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__I uint32_t RISR; /* Raw interrupt status */
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__I uint32_t TXOICR; /* TX FIFO overflow interrupt clear */
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__I uint32_t RXOICR; /* RX FIFO overflow interrupt clear */
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__I uint32_t RXUICR; /* RX FIFO underflow interrupt clear */
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__I uint32_t MSTICR; /* Multi-master interrupt clear */
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__I uint32_t ICR; /* Interrupt clear */
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__IO uint32_t DMACR; /* DMA control */
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__IO uint32_t DMATDLR; /* DMA TX data level */
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__IO uint32_t DMARDLR; /* DMA RX data level */
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__I uint32_t IDR; /* Identification */
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__I uint32_t SSI_COMP_VERSION; /* CoreKit version ID */
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__IO uint32_t DR[36]; /* Data register array */
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__IO uint32_t RX_SAMPLE_DLY; /* RX sample delay */
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} SPI_TypeDef;
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/** @} */
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/* AMEBAZ_SPIC */
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typedef struct {
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__IO uint32_t ctrlr0; /* Control register 0 */
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__IO uint32_t ctrlr1; /* Control register 1 */
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__IO uint32_t ssienr; /* SPI enable */
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__IO uint32_t mwcr; /* Reserved */
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__IO uint32_t ser; /* Slave enable */
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__IO uint32_t baudr; /* Baudrate select */
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__IO uint32_t txftlr; /* TX FIFO threshold level */
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__IO uint32_t rxftlr; /* RX FIFO threshold level */
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__IO uint32_t txflr; /* TX FIFO level */
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__IO uint32_t rxflr; /* RX FIFO level */
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__IO uint32_t sr; /* Status register */
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__IO uint32_t imr; /* Interrupt mask */
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__IO uint32_t isr; /* Interrupt status */
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__IO uint32_t risr; /* Raw interrupt status */
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__IO uint32_t txoicr; /* TX FIFO overflow interrupt clear */
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__IO uint32_t rxoicr; /* RX FIFO overflow interrupt clear */
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__IO uint32_t rxuicr; /* RX FIFO underflow interrupt clear */
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__IO uint32_t msticr; /* Master error interrupt clear */
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__IO uint32_t icr; /* Interrupt clear */
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__IO uint32_t dmacr; /* Reserved */
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__IO uint32_t dmatdlr; /* Reserved */
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__IO uint32_t dmardlr; /* Reserved */
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__IO uint32_t idr; /* Identification register */
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__IO uint32_t spi_flash_version; /* Version ID */
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union {
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__IO uint8_t byte;
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__IO uint16_t half;
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__IO uint32_t word;
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} dr[32]; /* Data register array */
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__IO uint32_t rd_fast_single; /* Flash fast read command */
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__IO uint32_t rd_dual_o; /* Flash dual output read */
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__IO uint32_t rd_dual_io; /* Flash dual I/O read */
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__IO uint32_t rd_quad_o; /* Flash quad output read */
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__IO uint32_t rd_quad_io; /* Flash quad I/O read */
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__IO uint32_t wr_single; /* Flash page program */
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__IO uint32_t wr_dual_i; /* Flash dual input program */
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__IO uint32_t wr_dual_ii; /* Flash dual addr/data program */
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__IO uint32_t wr_quad_i; /* Flash quad input program */
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__IO uint32_t wr_quad_ii; /* Flash quad addr/data program */
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__IO uint32_t wr_enable; /* Flash write enable */
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__IO uint32_t rd_status; /* Flash read status */
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__IO uint32_t ctrlr2; /* Control register 2 */
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__IO uint32_t fbaudr; /* Fast baudrate select */
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__IO uint32_t addr_length; /* Address length */
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__IO uint32_t auto_length; /* Auto address length */
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__IO uint32_t valid_cmd; /* Valid command */
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__IO uint32_t flash_size; /* Flash size */
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__IO uint32_t flush_fifo; /* Flush FIFO */
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} SPIC_TypeDef;
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/* AMEBAZ_ADC */
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typedef struct {
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__IO uint32_t FIFO_READ; /* FIFO read register for channels 0-3 */
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__IO uint32_t CONTROL; /* Main ADC control register */
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__IO uint32_t INTR_EN; /* Interrupt enable register */
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__IO uint32_t INTR_STS; /* Interrupt status register */
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__IO uint32_t COMP_VALUE_L; /* Compare values for channels 0-1 */
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__IO uint32_t COMP_VALUE_H; /* Compare values for channels 2-3 */
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__IO uint32_t COMP_SET; /* Compare configuration register */
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__IO uint32_t POWER; /* Power management register */
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__IO uint32_t ANAPAR_AD0; /* Analog parameters for channel 0 */
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__IO uint32_t ANAPAR_AD1; /* Analog parameters for channel 1 */
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__IO uint32_t ANAPAR_AD2; /* Analog parameters for channel 2 */
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__IO uint32_t ANAPAR_AD3; /* Analog parameters for channel 3 */
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__IO uint32_t ANAPAR_AD4; /* Analog parameters for channel 4 */
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__IO uint32_t ANAPAR_AD5; /* Analog parameters for channel 5 */
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__IO uint32_t CALI_DATA; /* Calibration data register */
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} ADC_TypeDef;
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/** @} */
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/* AMEBAZ_I2C */
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typedef struct {
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__IO uint32_t IC_CON; /* Control register */
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__IO uint32_t IC_TAR; /* Target address register */
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__IO uint32_t IC_SAR; /* Slave0 address register */
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__IO uint32_t IC_HS_MADDR; /* HS master mode code address */
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__IO uint32_t IC_DATA_CMD; /* RX/TX data buffer and command */
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__IO uint32_t IC_SS_SCL_HCNT; /* Standard speed SCL high count */
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__IO uint32_t IC_SS_SCL_LCNT; /* Standard speed SCL low count */
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__IO uint32_t IC_FS_SCL_HCNT; /* Fast speed SCL high count */
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__IO uint32_t IC_FS_SCL_LCNT; /* Fast speed SCL low count */
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__IO uint32_t IC_HS_SCL_HCNT; /* High speed SCL high count */
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__IO uint32_t IC_HS_SCL_LCNT; /* High speed SCL low count */
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__I uint32_t IC_INTR_STAT; /* Interrupt status */
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__IO uint32_t IC_INTR_MASK; /* Interrupt mask */
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__I uint32_t IC_RAW_INTR_STAT; /* Raw interrupt status */
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__IO uint32_t IC_RX_TL; /* Receive FIFO threshold */
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__IO uint32_t IC_TX_TL; /* Transmit FIFO threshold */
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__I uint32_t IC_CLR_INTR; /* Clear combined interrupts */
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__I uint32_t IC_CLR_RX_UNDER; /* Clear RX_UNDER interrupt */
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__I uint32_t IC_CLR_RX_OVER; /* Clear RX_OVER interrupt */
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__I uint32_t IC_CLR_TX_OVER; /* Clear TX_OVER interrupt */
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__I uint32_t IC_CLR_RD_REQ; /* Clear RD_REQ interrupt */
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__I uint32_t IC_CLR_TX_ABRT; /* Clear TX_ABRT interrupt */
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__I uint32_t IC_CLR_RX_DONE; /* Clear RX_DONE interrupt */
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__I uint32_t IC_CLR_ACTIVITY; /* Clear ACTIVITY interrupt */
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__I uint32_t IC_CLR_STOP_DET; /* Clear STOP_DET interrupt */
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__I uint32_t IC_CLR_START_DET; /* Clear START_DET interrupt */
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__I uint32_t IC_CLR_GEN_CALL; /* Clear GEN_CALL interrupt */
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__IO uint32_t IC_ENABLE; /* Enable register */
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__I uint32_t IC_STATUS; /* Status register */
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__I uint32_t IC_TXFLR; /* Transmit FIFO level */
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__I uint32_t IC_RXFLR; /* Receive FIFO level */
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__IO uint32_t IC_SDA_HOLD; /* SDA hold time length */
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__I uint32_t IC_TX_ABRT_SOURCE; /* Transmit abort status */
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__IO uint32_t IC_SLV_DATA_NACK_ONLY; /* Generate SLV_DATA_NACK */
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__IO uint32_t IC_DMA_CR; /* DMA control */
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__IO uint32_t IC_DMA_TDLR; /* DMA transmit data level */
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__IO uint32_t IC_DMA_RDLR; /* DMA receive data level */
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__IO uint32_t IC_SDA_SETUP; /* SDA setup */
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__IO uint32_t IC_ACK_GENERAL_CALL; /* ACK general call */
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__IO uint32_t IC_ENABLE_STATUS; /* Enable status */
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/* AmebaZ added New registers */
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__IO uint32_t IC_DMA_CMD; /* DMA command */
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__IO uint32_t IC_DMA_DAT_LEN; /* DMA transmit data length */
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__IO uint32_t IC_DMA_MOD; /* DMA mode */
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__IO uint32_t IC_SLEEP; /* Sleep control */
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__IO uint32_t IC_RSVD1[4]; /* Reserved field */
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__I uint32_t IC_RSVD2[4]; /* Reserved field */
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__I uint32_t IC_RSVD3[4]; /* Reserved field */
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__I uint32_t IC_RSVD4; /* Reserved field */
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__I uint32_t IC_CLR_ADDR_MATCH; /* Clear ADDR_MATCH interrupt */
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__I uint32_t IC_CLR_DMA_I2C_DONE; /* Clear DMA_I2C_DONE interrupt */
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__IO uint32_t IC_FILTER; /* Filter register */
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__I uint32_t IC_RSVD5; /* Reserved field */
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__IO uint32_t IC_SAR1; /* Slave1 address */
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__IO uint32_t IC_DATA_S1; /* Slave1 RX/TX data buffer */
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__I uint32_t IC_COMP_VERSION; /* Component version ID */
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} I2C_TypeDef;
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/** @} */
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/* AMEBAZ_I2S */
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typedef struct {
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__IO uint32_t IS_CTL; /* Main I2S control register */
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__IO uint32_t IS_TX_PAGE_PTR; /* TX page pointer */
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__IO uint32_t IS_RX_PAGE_PTR; /* RX page pointer */
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__IO uint32_t IS_SETTING; /* Page size and sample rate settings */
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__IO uint32_t IS_TX_MASK_INT; /* TX interrupt enable */
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__IO uint32_t IS_TX_STATUS_INT; /* TX interrupt status */
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__IO uint32_t IS_RX_MASK_INT; /* RX interrupt enable */
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__IO uint32_t IS_RX_STATUS_INT; /* RX interrupt status */
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__IO uint32_t IS_TX_PAGE_OWN[4]; /* TX page ownership bits */
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__IO uint32_t IS_RX_PAGE_OWN[4]; /* RX page ownership bits */
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} I2S_TypeDef;
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/** @} */
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/*
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* AMEBAZ_TIMER Register Declaration
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* TIM1 have 6 CCR registers: bit[15:0] is CCR, bit[31:24] is CCMR
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* TIM3 have 1 CCR registesr: bit[15:0] is CCR, bit[31:24] is CCMR
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* TIM5-8 dont have CCR register
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*/
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/**
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* @brief RTK TIM CCR
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*/
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typedef struct {
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__IO uint16_t CCRx; /*TIM capture/compare register */
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__IO uint8_t RSVD; /*TIM capture/compare rsvd register */
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__IO uint8_t CCMRx; /*TIM capture/compare register */
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} RTIM_CCR_TypeDef;
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/**
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* RTK Timer (RTIM) registers
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*/
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typedef struct {
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__IO uint32_t EN; /* Timer enable */
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__IO uint32_t CR; /* Main control settings */
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__IO uint32_t DIER; /* DMA/Interrupt configuration */
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__IO uint32_t SR; /* Status flags */
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__IO uint32_t EGR; /* Event generation control */
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__IO uint32_t CNT; /* Counter value */
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__IO uint32_t PSC; /* Clock prescaler */
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__IO uint32_t ARR; /* Auto-reload value */
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__IO uint32_t CCMRx[6]; /* Capture/Compare modes */
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} RTIM_TypeDef;
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/** @} */
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/* Real-Time Clock (RTC) registers */
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typedef struct {
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__IO uint32_t TR; /* Time value */
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__IO uint32_t CR; /* Control settings */
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__IO uint32_t ISR; /* Status and initialization */
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__IO uint32_t PRER; /* Clock prescaler */
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__IO uint32_t CALIBR; /* Calibration settings */
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__IO uint32_t ALMR1; /* Alarm 1 configuration */
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__IO uint32_t ALMR2; /* Alarm 2 configuration */
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__IO uint32_t WPR; /* Write protection */
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} RTC_TypeDef;
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/** @} */
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/* AMEBAZ_PINMUX */
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typedef struct {
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__IO uint32_t PADCTR[21]; /*Pad control register */
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} PINMUX_TypeDef;
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/** @} */
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/* AMEBAZ_IPSEC */
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typedef struct {
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__IO uint32_t IPSSDAR; /* Source Descriptor Starting Address Register */
|
||||
__IO uint32_t IPSDDAR; /* Destination Descriptor Starting Address Register */
|
||||
__IO uint32_t IPSCSR; /* Command/Status Register */
|
||||
__IO uint32_t IPSCTR; /* Control Register */
|
||||
} IPSEC_TypeDef;
|
||||
/** @} */
|
||||
|
||||
/* AMEBAZ_USOC */
|
||||
typedef struct {
|
||||
__IO uint32_t SIE_CR; /* SIE control */
|
||||
__IO uint32_t CLK_RST_CTRL; /* Clock and reset control */
|
||||
__IO uint32_t CHANN_CTRL; /* Channel control */
|
||||
__IO uint32_t BUFF_SIZE_CTRL; /* TX/RX buffer size control */
|
||||
__IO uint32_t TXBD_BAR; /* TX buffer descriptor base address */
|
||||
__IO uint32_t RXBD_BAR; /* RX buffer descriptor base address */
|
||||
__IO uint32_t RING_SIZE_CTRL; /* Ring size control */
|
||||
__IO uint32_t RSVD1; /* Reserved */
|
||||
__I uint32_t TXBD_HW_IDX; /* TX hardware index */
|
||||
__IO uint32_t TXBD_SW_IDX; /* TX software index */
|
||||
__I uint32_t RXBD_HW_IDX; /* RX hardware index */
|
||||
__IO uint32_t RXBD_SW_IDX; /* RX software index */
|
||||
__IO uint32_t INTR_MASK; /* Interrupt mask */
|
||||
__IO uint32_t INTR_CLR; /* Interrupt clear */
|
||||
__IO uint32_t INTR_STAT; /* Interrupt status */
|
||||
__IO uint32_t RSVD2; /* Reserved */
|
||||
__IO uint32_t TX_MIT; /* TX mitigation */
|
||||
__IO uint32_t RX_MIT; /* RX mitigation */
|
||||
__IO uint32_t RSVD3[2]; /* Reserved */
|
||||
__IO uint32_t IOREG_MAR; /* Host device access */
|
||||
__IO uint32_t RSVD4[3]; /* Reserved */
|
||||
__IO uint32_t TX_MAIN_BUF_CTRL; /* TX main buffer control */
|
||||
__IO uint32_t TX_DEST_BUF_CTRL; /* TX destination buffer control */
|
||||
__IO uint32_t RX_MAIN_BUF_CTRL; /* RX main buffer control */
|
||||
__IO uint32_t RX_SRC_BUF_CTRL; /* RX source buffer control */
|
||||
__IO uint32_t TX_STUCK_TIMER; /* TX stuck timer */
|
||||
__IO uint32_t RX_STUCK_TIMER; /* RX stuck timer */
|
||||
__IO uint32_t QOS_CTRL; /* QoS control */
|
||||
} USOC_REG_TypeDef;
|
||||
|
||||
/**
|
||||
* NCO32k (Numerically Controlled Oscillator) peripheral structure
|
||||
* Controls and monitors the 32KHz clock generation and calibration system
|
||||
*/
|
||||
typedef struct {
|
||||
__IO uint32_t CLK_INFO; // [23:0] Unregulated clock frequency value
|
||||
// [24] 32K clock output ready flag
|
||||
// [25] 32K calibration ready flag
|
||||
|
||||
__IO uint32_t CLK_OUT; // Expected frequency of NCO calibration output clock
|
||||
|
||||
__IO uint32_t CLK_REF; // Lower 32 bits of reference clock frequency
|
||||
// Used for clock output generation and input clock
|
||||
// monitoring (ASIC: OSC8M, FPGA: 128K)
|
||||
|
||||
__IO uint32_t CTRL; // [9:0] Reference clock frequency (upper 10 bits)
|
||||
// [16] 32K enable
|
||||
// [17] Reference clock enable
|
||||
// [23:20] 32K monitor
|
||||
// [30:24] 32K threshold
|
||||
} NCO32k_TypeDef;
|
||||
|
||||
/*
|
||||
* @defgroup AMEBAZ_NCO8M
|
||||
* @{
|
||||
* @brief AMEBAZ_NCO8M Register Declaration
|
||||
* @note [0]: function enable
|
||||
* @note [15:1]: expected frequency of nco output clk, unit is 1KHz
|
||||
* @note [31:16] frequency of nco input clk, unit is 1KHz
|
||||
*/
|
||||
typedef struct {
|
||||
__IO uint32_t NCOReg;
|
||||
} NCO8M_TypeDef;
|
||||
/** @} */
|
||||
|
||||
/* AMEBAZ_BACKUP_REG */
|
||||
typedef struct {
|
||||
__IO uint32_t DWORD[4]; /* 0x138 */
|
||||
} BACKUP_REG_TypeDef;
|
||||
/** @} */
|
||||
|
||||
/* AMEBAZ_CACHE Register Declaration */
|
||||
typedef struct {
|
||||
__IO uint32_t SPICC_EN; /* Enable control */
|
||||
__IO uint32_t SPICC_FLUSH; /* Cache flush control */
|
||||
__IO uint32_t SPICC_INTR; /* Interrupt status/control */
|
||||
__IO uint32_t SPICC_RST_CUNT; /* Reset counter */
|
||||
__IO uint32_t SPICC_RD_EVT_CUNT; /* Read events counter */
|
||||
__IO uint32_t SPICC_HIT_EVT_CUNT; /* Cache hit counter */
|
||||
__IO uint32_t SPICC_HIT_LSTW_EVT_CUNT; /* Last-way hit counter */
|
||||
__IO uint32_t SPICC_RD_PEND_CUNT; /* Pending read counter */
|
||||
} SPIC_CACHE_TypeDef;
|
||||
/** @} */
|
||||
|
||||
/* Control register definitions for system-level configurations */
|
||||
typedef struct {
|
||||
/* 0x0000 - Power/Isolation Control */
|
||||
union {
|
||||
struct {
|
||||
__IO uint16_t PWR_CTRL; /* 0x0000 */
|
||||
__IO uint16_t ISO_CTRL; /* 0x0002 */
|
||||
} PWR_ISO;
|
||||
__IO uint32_t PWR_ISO_CTRL; /* 0x0000 */
|
||||
};
|
||||
|
||||
uint32_t RESERVED0[1]; /* 0x0004 */
|
||||
__IO uint32_t FUNC_EN; /* 0x0008 */
|
||||
__IO uint32_t CLK_CTRL0; /* 0x0010 */
|
||||
__IO uint32_t CLK_CTRL1; /* 0x0014 */
|
||||
|
||||
uint32_t RESERVED1[2]; /* 0x0018-0x001C */
|
||||
|
||||
/* EFUSE System Configuration Registers */
|
||||
__IO uint32_t EFUSE_SYSCFG[8]; /* 0x0020-0x003C */
|
||||
|
||||
__IO uint32_t REGU_CTRL0; /* 0x0040 */
|
||||
uint32_t RESERVED2[1]; /* 0x0044 */
|
||||
__IO uint32_t SWR_CTRL0; /* 0x0048 */
|
||||
__IO uint32_t SWR_CTRL1; /* 0x004C */
|
||||
|
||||
uint32_t RESERVED3[4]; /* 0x0050-0x005C */
|
||||
|
||||
/* Crystal Control Registers */
|
||||
__IO uint32_t XTAL_CTRL0; /* 0x0060 */
|
||||
__IO uint32_t XTAL_CTRL1; /* 0x0064 */
|
||||
__IO uint32_t XTAL_CTRL2; /* 0x0068 */
|
||||
|
||||
uint32_t RESERVED4[1]; /* 0x006C */
|
||||
|
||||
/* System PLL Control Registers */
|
||||
__IO uint32_t SYSPLL_CTRL0; /* 0x0070 */
|
||||
__IO uint32_t SYSPLL_CTRL1; /* 0x0074 */
|
||||
__IO uint32_t SYSPLL_CTRL2; /* 0x0078 */
|
||||
__IO uint32_t SYSPLL_CTRL3; /* 0x007C */
|
||||
|
||||
uint32_t RESERVED5[4]; /* 0x0080-0x008C */
|
||||
|
||||
__IO uint32_t ANA_TIM_CTRL; /* 0x0090 */
|
||||
__IO uint32_t DSLP_TIM_CTRL; /* 0x0094 */
|
||||
__IO uint32_t DSLP_TIM_CAL_CTRL; /* 0x0098 */
|
||||
|
||||
uint32_t RESERVED6[2]; /* 0x009C-0x00A0 */
|
||||
|
||||
__IO uint32_t DEBUG_CTRL; /* 0x00A0 */
|
||||
__IO uint32_t PINMUX_CTRL; /* 0x00A4 */
|
||||
__IO uint32_t GPIO_DSTBY_WAKE_CTRL0; /* 0x00A8 */
|
||||
__IO uint32_t GPIO_DSTBY_WAKE_CTRL1; /* 0x00AC */
|
||||
|
||||
uint32_t RESERVED7[3]; /* 0x00B0-0x00B8 */
|
||||
|
||||
__IO uint32_t DEBUG_REG; /* 0x00BC */
|
||||
|
||||
uint32_t RESERVED8[8]; /* 0x00C0-0x00DC */
|
||||
|
||||
__IO uint32_t EEPROM_CTRL0; /* 0x00E0 */
|
||||
__IO uint32_t EEPROM_CTRL1; /* 0x00E4 */
|
||||
__IO uint32_t EFUSE_CTRL; /* 0x00E8 */
|
||||
__IO uint32_t EFUSE_TEST; /* 0x00EC */
|
||||
__IO uint32_t OSC32K_CTRL; /* 0x00F0 */
|
||||
__IO uint32_t OSC32K_RCAL; /* 0x00F4 */
|
||||
__IO uint32_t DSTBY_INFO0; /* 0x00F8 */
|
||||
__IO uint32_t DSTBY_INFO1; /* 0x00FC */
|
||||
__IO uint32_t SLP_WAKE_EVENT_MSK0; /* 0x0100 */
|
||||
__IO uint32_t SLP_WAKE_EVENT_MSK1; /* 0x0104 */
|
||||
__IO uint32_t SLP_WAKE_EVENT_STATUS0; /* 0x0108 */
|
||||
__IO uint32_t SLP_WAKE_EVENT_STATUS1; /* 0x010C */
|
||||
__IO uint32_t SNF_WAKE_EVENT_MSK0; /* 0x0110 */
|
||||
__IO uint32_t SNF_WAKE_EVENT_STATUS; /* 0x0114 */
|
||||
__IO uint32_t PWRMGT_CTRL; /* 0x0118 */
|
||||
|
||||
uint32_t RESERVED9[1]; /* 0x011C */
|
||||
|
||||
__IO uint32_t PWRMGT_OPTION; /* 0x0120 */
|
||||
__IO uint32_t PWRMGT_OPTION_EXT; /* 0x0124 */
|
||||
|
||||
uint32_t RESERVED10[2]; /* 0x0128-0x012C */
|
||||
|
||||
__IO uint32_t DSLP_WEVENT; /* 0x0130 */
|
||||
__IO uint32_t PERI_MONITOR; /* 0x0134 */
|
||||
__IO uint32_t NORESET_FF; /* 0x0138 */
|
||||
|
||||
uint32_t RESERVED11[45]; /* 0x013C-0x01EC */
|
||||
|
||||
__IO uint32_t SYSTEM_CFG0; /* 0x01F0 */
|
||||
__IO uint32_t SYSTEM_CFG1; /* 0x01F4 */
|
||||
__IO uint32_t SYSTEM_CFG2; /* 0x01F8 */
|
||||
} SYSTEM_CTRL_TypeDef;
|
||||
|
||||
/* Peripheral and clock control register definitions */
|
||||
typedef struct {
|
||||
__IO uint32_t PEON_PWR_CTRL; /* 0x0200 */
|
||||
__IO uint32_t PON_ISO_CTRL; /* 0x0204 */
|
||||
uint32_t RESERVED0[2]; /* 0x0208-0x020C */
|
||||
__IO uint32_t SOC_FUNC_EN; /* 0x0210 */
|
||||
__IO uint32_t SOC_HCI_COM_FUNC_EN; /* 0x0214 */
|
||||
__IO uint32_t SOC_PERI_FUNC0_EN; /* 0x0218 */
|
||||
__IO uint32_t SOC_PERI_FUNC1_EN; /* 0x021C */
|
||||
__IO uint32_t SOC_PERI_BD_FUNC0_EN; /* 0x0220 */
|
||||
uint32_t RESERVED1[3]; /* 0x0224-0x022C */
|
||||
__IO uint32_t PESOC_CLK_CTRL; /* 0x0230 */
|
||||
__IO uint32_t PESOC_PERI_CLK_CTRL0; /* 0x0234 */
|
||||
__IO uint32_t PESOC_PERI_CLK_CTRL1; /* 0x0238 */
|
||||
__IO uint32_t PESOC_CLK_CTRL3; /* 0x023C */
|
||||
__IO uint32_t PESOC_HCI_CLK_CTRL0; /* 0x0240 */
|
||||
__IO uint32_t PESOC_COM_CLK_CTRL1; /* 0x0244 */
|
||||
__IO uint32_t PESOC_HW_ENG_CLK_CTRL; /* 0x0248 */
|
||||
uint32_t RESERVED2[1]; /* 0x024C */
|
||||
__IO uint32_t PESOC_CLK_SEL; /* 0x0250 */
|
||||
uint32_t RESERVED3[6]; /* 0x0254-0x0268 */
|
||||
__IO uint32_t UART_NCO_CTRL; /* 0x026C */
|
||||
uint32_t RESERVED4[1]; /* 0x0270 */
|
||||
__IO uint32_t OSC32K_REG_CTRL0; /* 0x0274 */
|
||||
__IO uint32_t OSC32K_REG_CTRL1; /* 0x0278 */
|
||||
__IO uint32_t THERMAL_METER_CTRL; /* 0x027C */
|
||||
__IO uint32_t GPIO_PINMUX_CTRL[24]; /* 0x0280-0x02DC */
|
||||
__IO uint32_t PON_PINMUX_CTRL; /* 0x02E0 */
|
||||
uint32_t RESERVED5[6]; /* 0x02E4-0x02F8 */
|
||||
__IO uint32_t FW_PPROTECT_KEY_CTRL; /* 0x02FC */
|
||||
uint32_t RESERVED6[1]; /* 0x0300 */
|
||||
__IO uint32_t PESOC_SOC_CTRL; /* 0x0304 */
|
||||
} PERI_ON_TypeDef;
|
||||
|
||||
/* GPIO (General Purpose Input/Output) register definitions */
|
||||
typedef struct {
|
||||
__IO uint32_t DR; /* Data Register */
|
||||
__IO uint32_t DDR; /* Direction Register */
|
||||
__IO uint32_t CTRL; /* Control Register */
|
||||
} GPIO_Port_TypeDef;
|
||||
|
||||
typedef struct {
|
||||
GPIO_Port_TypeDef PORT[4]; /*GPIO IP have 4 ports */
|
||||
__IO uint32_t INT_EN; /* GPIO interrupt enable register */
|
||||
__IO uint32_t INT_MASK; /* GPIO interrupt mask register */
|
||||
__IO uint32_t INT_TYPE; /* interrupt type(level/edge) register */
|
||||
__IO uint32_t INT_POLARITY; /* interrupt polarity(Active low/high) register */
|
||||
__IO uint32_t INT_STATUS; /* interrupt status register */
|
||||
__IO uint32_t INT_RAWSTATUS; /* interrupt status without mask register */
|
||||
__IO uint32_t DEBOUNCE; /* interrupt signal debounce register */
|
||||
__IO uint32_t PORTA_EOI; /* clear interrupt register */
|
||||
__IO uint32_t EXT_PORT[4]; /* GPIO IN read or OUT read back register */
|
||||
__IO uint32_t LSSYNC; /* level-sensitive synchronization enable register */
|
||||
__IO uint32_t IDCODE; /* GPIO ID code register */
|
||||
__IO uint32_t RSVD2; /* Reserved */
|
||||
__IO uint32_t VERIDCODE; /* component Version register */
|
||||
__IO uint32_t CONFIG2; /* GPIO configuration Register 2 */
|
||||
__IO uint32_t CONFIG1; /* GPIO configuration Register 1 */
|
||||
} GPIO_TypeDef;
|
||||
|
||||
/* Peripheral memory map */
|
||||
#define SYSTEM_CTRL_BASE 0x40000000
|
||||
#define PERI_ON_BASE (SYSTEM_CTRL_BASE + 0x200)
|
||||
|
||||
#define VENDOR_REG_BASE 0x40002800
|
||||
#define SPI_FLASH_BASE 0x08000000
|
||||
|
||||
#define NCO1_REG_BASE 0x40000080
|
||||
#define BACKUP_REG_BASE 0x40000138
|
||||
#define NCO2_REG_BASE 0x4000026C
|
||||
#define PINMUX_REG_BASE 0x40000280
|
||||
|
||||
#define GPIO_REG_BASE 0x40001000
|
||||
#define TIMER_REG_BASE 0x40002000
|
||||
#define LOG_UART_REG_BASE 0x40003000
|
||||
#define RTC_BASE 0x40003400
|
||||
#define SPIC_CACHE_BASE 0x40003C00
|
||||
#define ADC_REG_BASE 0x40010000
|
||||
#define SPI_FLASH_CTRL_BASE 0x40020000
|
||||
#define UART0_REG_BASE 0x40040000
|
||||
#define UART1_REG_BASE 0x40040400
|
||||
#define UART2_REG_BASE LOG_UART_REG_BASE
|
||||
#define SPI0_REG_BASE 0x40042000
|
||||
#define SPI1_REG_BASE 0x40042400
|
||||
#define I2C0_REG_BASE 0x40044000
|
||||
#define I2C1_REG_BASE 0x40044400
|
||||
#define SDIO_DEVICE_REG_BASE 0x40050000
|
||||
#define GDMA0_REG_BASE 0x40060000
|
||||
#define GDMA1_REG_BASE 0x40061000
|
||||
#define I2S0_REG_BASE 0x40062000
|
||||
#define CRYPTO_REG_BASE 0x40070000
|
||||
#define WIFI_REG_BASE 0x40080000
|
||||
#define SIE_REG_BASE 0x400C0000
|
||||
#define USOC_REG_BASE 0x400C2000
|
||||
#define GDMA1_REG_OFF 0x1000
|
||||
|
||||
#define TIM0_BASE (TIMER_REG_BASE)
|
||||
#define TIM1_BASE (TIMER_REG_BASE + 0x040)
|
||||
#define TIM2_BASE (TIMER_REG_BASE + 0x080)
|
||||
#define TIM3_BASE (TIMER_REG_BASE + 0x0C0)
|
||||
#define TIM4_BASE (TIMER_REG_BASE + 0x100)
|
||||
#define TIM5_BASE (TIMER_REG_BASE + 0x140)
|
||||
|
||||
/* Peripheral declaration */
|
||||
#define SYSTEM_CTRL ((SYSTEM_CTRL_TypeDef *)SYSTEM_CTRL_BASE)
|
||||
#define PERI_ON ((PERI_ON_TypeDef *)PERI_ON_BASE)
|
||||
|
||||
#define UART0 ((UART_TypeDef *)UART0_REG_BASE)
|
||||
#define UART1 ((UART_TypeDef *)UART1_REG_BASE)
|
||||
#define UART2 ((UART_TypeDef *)LOG_UART_REG_BASE)
|
||||
#define SPI0 ((SPI_TypeDef *)SPI0_REG_BASE)
|
||||
#define SPI1 ((SPI_TypeDef *)SPI1_REG_BASE)
|
||||
#define SPIC ((SPIC_TypeDef *)SPI_FLASH_CTRL_BASE)
|
||||
#define ADC ((ADC_TypeDef *)ADC_REG_BASE)
|
||||
#define I2C0 ((I2C_TypeDef *)I2C0_REG_BASE)
|
||||
#define I2C1 ((I2C_TypeDef *)I2C1_REG_BASE)
|
||||
#define I2S ((I2S_TypeDef *)I2S0_REG_BASE)
|
||||
#define TIM0 ((RTIM_TypeDef *)TIM0_BASE)
|
||||
#define TIM1 ((RTIM_TypeDef *)TIM1_BASE)
|
||||
#define TIM2 ((RTIM_TypeDef *)TIM2_BASE)
|
||||
#define TIM3 ((RTIM_TypeDef *)TIM3_BASE)
|
||||
#define TIM4 ((RTIM_TypeDef *)TIM4_BASE)
|
||||
#define TIM5 ((RTIM_TypeDef *)TIM5_BASE)
|
||||
#define RTC ((RTC_TypeDef *)RTC_BASE)
|
||||
#define PINMUX ((PINMUX_TypeDef *)PINMUX_REG_BASE)
|
||||
#define IPSEC ((IPSEC_TypeDef *)CRYPTO_REG_BASE)
|
||||
#define USOC_REG ((USOC_REG_TypeDef *)USOC_REG_BASE)
|
||||
#define NCO32k ((NCO32k_TypeDef *)NCO1_REG_BASE)
|
||||
#define NCO8M ((NCO8M_TypeDef *)NCO2_REG_BASE)
|
||||
#define BACKUP_REG ((BACKUP_REG_TypeDef *)BACKUP_REG_BASE)
|
||||
#define SPIC_CACHE ((SPIC_CACHE_TypeDef *)SPIC_CACHE_BASE)
|
||||
|
||||
#define GPIOA ((GPIO_Port_TypeDef *)(GPIO_REG_BASE + 0x00))
|
||||
#define GPIOB ((GPIO_Port_TypeDef *)(GPIO_REG_BASE + 0x0C))
|
||||
#define GPIOC ((GPIO_Port_TypeDef *)(GPIO_REG_BASE + 0x18))
|
||||
|
||||
#define GPIO_COMMON ((GPIO_Common_TypeDef *)(GPIO_REG_BASE + 0x30))
|
||||
|
||||
/* rtl8711b_peri_on.h */
|
||||
// 2 0x200 REG_PEON_PWR_CTRL
|
||||
#define BIT_SOC_UAHV_EN (1 << 2)
|
||||
#define BIT_SOC_UALV_EN (1 << 1)
|
||||
#define BIT_SOC_USBD_EN (1 << 0)
|
||||
|
||||
// 2 0x210 REG_SOC_FUNC_EN
|
||||
#define BIT_SOC_BOOT_FROM_JTAG (1 << 31)
|
||||
#define BIT_SOC_UNLOCK_FROM_JTAG (1 << 30)
|
||||
#define BIT_SOC_WAKE_FROM_PS (1 << 29)
|
||||
#define BIT_SOC_PATCH_FUNC0 (1 << 28)
|
||||
#define BIT_SOC_PATCH_FUNC1 (1 << 27)
|
||||
#define BIT_SOC_PATCH_FUNC2 (1 << 26)
|
||||
|
||||
#define BIT_SOC_XMODEM_PAGE_PG (1 << 25)
|
||||
#define BIT_SOC_XMODEM_FLASH_EMPTY (1 << 24)
|
||||
|
||||
#define BIT_SOC_SECURITY_ENGINE_EN (1 << 20)
|
||||
#define BIT_SOC_GTIMER_EN (1 << 16)
|
||||
#define BIT_SOC_GDMA1_EN (1 << 14)
|
||||
#define BIT_SOC_GDMA0_EN (1 << 13)
|
||||
#define BIT_SOC_LOG_UART_EN (1 << 12)
|
||||
#define BIT_SOC_CPU_EN (1 << 8)
|
||||
#define BIT_SOC_MEM_CTRL_EN (1 << 6)
|
||||
#define BIT_SOC_FLASH_EN (1 << 4)
|
||||
#define BIT_SOC_LXBUS_EN (1 << 2)
|
||||
#define BIT_SOC_OCP_EN (1 << 1)
|
||||
#define BIT_SOC_FUN_EN (1 << 0)
|
||||
|
||||
// 2 0x0214 REG_SOC_HCI_COM_FUNC_EN
|
||||
#define BIT_SOC_HCI_WL_MACON_EN (1 << 16)
|
||||
#define BIT_SOC_HCI_SM_SEL (1 << 13)
|
||||
#define BIT_SOC_HCI_OTG_RST_MUX (1 << 5)
|
||||
#define BIT_SOC_HCI_OTG_EN (1 << 4)
|
||||
#define BIT_SOC_HCI_SDIOD_ON_RST_MUX (1 << 3)
|
||||
#define BIT_SOC_HCI_SDIOD_OFF_EN (1 << 1)
|
||||
#define BIT_SOC_HCI_SDIOD_ON_EN (1 << 0)
|
||||
|
||||
// 2 0x0218 REG_SOC_PERI_FUNC0_EN
|
||||
#define BIT_PERI_I2S0_EN (1 << 24)
|
||||
#define BIT_PERI_I2C1_EN (1 << 17)
|
||||
#define BIT_PERI_I2C0_EN (1 << 16)
|
||||
#define BIT_PERI_SPI1_EN (1 << 9)
|
||||
#define BIT_PERI_SPI0_EN (1 << 8)
|
||||
#define BIT_PERI_UART2_EN (1 << 2)
|
||||
#define BIT_PERI_UART1_EN (1 << 1)
|
||||
#define BIT_PERI_UART0_EN (1 << 0)
|
||||
|
||||
// 2 0x021C REG_SOC_PERI_FUNC1_EN
|
||||
#define BIT_PERI_GPIO_EN (1 << 8)
|
||||
#define BIT_PERI_ADC0_EN (1 << 0)
|
||||
|
||||
// 2 0x0220 REG_SOC_PERI_BD_FUNC0_EN
|
||||
#define BIT_PERI_UART2_BD_EN (1 << 2)
|
||||
#define BIT_PERI_UART1_BD_EN (1 << 1)
|
||||
#define BIT_PERI_UART0_BD_EN (1 << 0)
|
||||
|
||||
// 2 0x0230 REG_PESOC_CLK_CTRL
|
||||
#define BIT_SOC_SLPCK_BTCMD_EN (1 << 29)
|
||||
#define BIT_SOC_ACTCK_BTCMD_EN (1 << 28)
|
||||
#define BIT_SOC_ACTCK_GPIO_EN (1 << 24)
|
||||
#define BIT_SOC_ACTCK_GDMA1_EN (1 << 18)
|
||||
#define BIT_SOC_ACTCK_GDMA0_EN (1 << 16)
|
||||
#define BIT_SOC_ACTCK_TIMER_EN (1 << 14)
|
||||
#define BIT_SOC_ACTCK_LOG_UART_EN (1 << 12)
|
||||
#define BIT_SOC_ACTCK_FLASH_EN (1 << 8)
|
||||
#define BIT_SOC_ACTCK_VENDOR_REG_EN (1 << 6)
|
||||
#define BIT_SOC_ACTCK_TRACE_EN (1 << 4)
|
||||
#define BIT_SOC_CKE_PLFM (1 << 2)
|
||||
#define BIT_SOC_CKE_OCP (1 << 0)
|
||||
|
||||
// 2 0x0234 REG_PESOC_PERI_CLK_CTRL0
|
||||
#define BIT_SOC_ACTCK_SPI1_EN (1 << 18)
|
||||
#define BIT_SOC_ACTCK_SPI0_EN (1 << 16)
|
||||
#define BIT_SOC_ACTCK_UART1_EN (1 << 2)
|
||||
#define BIT_SOC_ACTCK_UART0_EN (1 << 0)
|
||||
|
||||
// 2 0x0238 REG_PESOC_PERI_CLK_CTRL1
|
||||
#define BIT_SOC_ACTCK_ADC_EN (1 << 24)
|
||||
#define BIT_SOC_ACTCK_I2S_EN (1 << 16)
|
||||
#define BIT_SOC_ACTCK_I2C1_EN (1 << 2)
|
||||
#define BIT_SOC_ACTCK_I2C0_EN (1 << 0)
|
||||
|
||||
// 2 0x0240 REG_PESOC_HCI_CLK_CTRL0
|
||||
#define BIT_SOC_ACTCK_OTG_EN (1 << 4)
|
||||
#define BIT_SOC_ACTCK_SDIO_HST_EN \
|
||||
(1 << 2) // SDIO_HST clock enable in CPU run mode
|
||||
#define BIT_SOC_ACTCK_SDIO_DEV_EN \
|
||||
(1 << 0) // SDIO_DEV clock enable in CPU run mode
|
||||
|
||||
/* REG_PESOC_CLK_SEL 0x0250 */
|
||||
#define BIT_SHIFT_PESOC_UART1_SCLK_SEL 26
|
||||
/* [27:26] uart1 rx clock, 01: osc 8m; 00: xtal; 10: xtal nco */
|
||||
#define BIT_MASK_PESOC_UART1_SCLK_SEL 0x03
|
||||
#define BIT_SHIFT_PESOC_UART0_SCLK_SEL 19
|
||||
/* [20:19] uart0 rx clock, 01: osc 8m; 00: xtal; 10: xtal nco */
|
||||
#define BIT_MASK_PESOC_UART0_SCLK_SEL 0x03
|
||||
|
||||
/* 1: enable to generate flash clock (with phase shift) divided by 500M pll
|
||||
* clock, HW detect this signal's rising edge to start the phase shift clock
|
||||
* division circuit. */
|
||||
#define BIT_FLASH_CK_PS_DIV_EN (1 << 25)
|
||||
/* 1: enable to generate flash clock (no phase shift) divided by 500M pll clock,
|
||||
* HW detect this signal's rising edge to start the no phase shift division
|
||||
* circuit. */
|
||||
#define BIT_FLASH_CK_DIV_EN (1 << 24)
|
||||
/* 1: delay flash sout for calibration; 0: bypass flash sout to spic */
|
||||
#define BIT_FLASH_CAL_EN (1 << 23)
|
||||
#define BIT_SHIFT_FLASH_CK_PS_INT 12
|
||||
/* [14:12] Flash clock phase shift in units of 500M pll clock cycels */
|
||||
#define BIT_MASK_FLASH_CK_PS_INT 0x03
|
||||
/* ready flag of Flash clock with phase shift, Read only */
|
||||
#define BIT_FLASH_PS_DIV_RDY (1 << 7)
|
||||
/* ready flag of Flash clock, Read only */
|
||||
#define BIT_FLASH_DIV_RDY (1 << 6)
|
||||
#define BIT_SHIFT_PESOC_TRACE_CK_SEL 4
|
||||
/* [5:4] "Trace clock select0: 12.5MH1: 25MHz2: 50MHz3: 100MHz" */
|
||||
#define BIT_MASK_PESOC_TRACE_CK_SEL 0x03
|
||||
/* "Only valid when r_FLASH_DIV_FRAC= 1, it decides the duty cycle of flash
|
||||
* clock when not divided by integer1: duty cycle > 50% ; 0: duty cycle < 50%"
|
||||
*/
|
||||
#define BIT_FLASH_DIV_HIGH_FRAC (1 << 3)
|
||||
/* "Flash clock division ratio, fractional part0: no fraction, only divided by
|
||||
* integer set by bit[1:0], 1: 0.5" */
|
||||
#define BIT_FLASH_DIV_FRAC (1 << 2)
|
||||
#define BIT_SHIFT_DIV_INT 0
|
||||
/* [1:0] "Flash clock division ratio, integrate part0: divided by 21: divided by
|
||||
* 32: divided by 43: divided by 5" */
|
||||
#define BIT_MASK_FLASH_DIV_INT 0x03
|
||||
|
||||
// 0x0244 REG_PESOC_COM_CLK_CTRL1
|
||||
#define BIT_SOC_ACTCK_SECURITY_ENG_EN (1 << 4)
|
||||
// spec name is wrong (BIT_SOC_ACTCK_WL_EN)
|
||||
#define BIT_SOC_ACTCK_LXBUS_EN (1 << 0)
|
||||
|
||||
// 0x02E0 REG_PON_PINMUX_CTRL
|
||||
#define BIT_HCI_SDIOD_PIN_EN (1 << 0)
|
||||
|
||||
// 0x0304 REG_PESOC_SOC_CTRL
|
||||
#define BIT_PESOC_LX_SLV_SWAP_SEL (1 << 10)
|
||||
#define BIT_PESOC_LX_MST_SWAP_SEL (1 << 9)
|
||||
#define BIT_PESOC_LX_WL_SWAP_SEL (1 << 8)
|
||||
|
||||
// 0x2FC REG_FW_PPROTECT_KEY_CTRL
|
||||
#define BIT_RDP_EN (1 << 3) /* load from efuse */
|
||||
#define BIT_RDP_EN_LOAD (1 << 2)
|
||||
#define BIT_RDP_KEY_REQ (1 << 1)
|
||||
#define BIT_OTF_KEY_REQ (1 << 0)
|
||||
|
||||
/* rtl8711b_pinmux.h */
|
||||
#define _PA_0 (0x00)
|
||||
#define _PA_1 (0x01)
|
||||
#define _PA_2 (0x02)
|
||||
#define _PA_3 (0x03)
|
||||
#define _PA_4 (0x04)
|
||||
#define _PA_5 (0x05)
|
||||
#define _PA_6 (0x06)
|
||||
#define _PA_7 (0x07)
|
||||
#define _PA_8 (0x08)
|
||||
#define _PA_9 (0x09)
|
||||
#define _PA_10 (0x0A)
|
||||
#define _PA_11 (0x0B)
|
||||
#define _PA_12 (0x0C)
|
||||
#define _PA_13 (0x0D)
|
||||
#define _PA_14 (0x0E)
|
||||
#define _PA_15 (0x0F)
|
||||
#define _PA_16 (0x10)
|
||||
#define _PA_17 (0x11)
|
||||
#define _PA_18 (0x12)
|
||||
#define _PA_19 (0x13)
|
||||
#define _PA_20 (0x14)
|
||||
#define _PA_21 (0x15)
|
||||
#define _PA_22 (0x16)
|
||||
#define _PA_23 (0x17)
|
||||
#define _PA_24 (0x18)
|
||||
#define _PA_25 (0x19)
|
||||
#define _PA_26 (0x1A)
|
||||
#define _PA_27 (0x1B)
|
||||
#define _PA_28 (0x1C)
|
||||
#define _PA_29 (0x1D)
|
||||
#define _PA_30 (0x1E)
|
||||
#define _PA_31 (0x1F)
|
||||
#define _PB_0 (0x20)
|
||||
#define _PB_1 (0x21)
|
||||
#define _PB_2 (0x22)
|
||||
#define _PB_3 (0x23)
|
||||
#define _PB_4 (0x24)
|
||||
#define _PB_5 (0x25)
|
||||
#define _PB_6 (0x26)
|
||||
#define _PB_7 (0x27)
|
||||
#define _PB_8 (0x28)
|
||||
#define _PNC (0xFFFFFFFF)
|
||||
|
||||
// PINMUX function modes
|
||||
#define PINMUX_FN_GPIO 0x100 // Normal GPIO mode
|
||||
#define PINMUX_FN_UART 0x101 // UART function
|
||||
#define PINMUX_FN_SPIM 0x102 // SPI1 function (why diff function code?)
|
||||
#define PINMUX_FN_SPIS 0x103 // SPI0 function
|
||||
#define PINMUX_FN_SPIF 0x104 // SPI Flash interface
|
||||
#define PINMUX_FN_I2C 0x105 // I2C function
|
||||
#define PINMUX_FN_SDIO 0x106 // SDIO function
|
||||
#define PINMUX_FN_PWM 0x107 // PWM
|
||||
#define PINMUX_FN_TIMINPUT 0x107 // PWM
|
||||
#define PINMUX_FN_SWD 0x108
|
||||
#define PINMUX_FN_EXT32K 0x108
|
||||
#define PINMUX_FN_RTCOUT 0x108
|
||||
#define PINMUX_FN_SWD 0x108 // SWD/JTAG function
|
||||
#define PINMUX_FN_I2S 0x109 // I2S function
|
||||
#define PINMUX_FN_COEX_EXT32K 0x10a
|
||||
#define PINMUX_FN_BTCOEX 0x10a
|
||||
#define PINMUX_FN_WLLED 0x10a
|
||||
|
||||
#define PAD_DRV_STRENGTH_0 (0x00000000 << 9)
|
||||
#define PAD_DRV_STRENGTH_1 (0x00000001 << 9)
|
||||
#define PAD_DRV_STRENGTH_2 (0x00000002 << 9)
|
||||
#define PAD_DRV_STRENGTH_3 (0x00000003 << 9)
|
||||
#define PAD_DRV_STRENGTH_4 (0x00000004 << 9)
|
||||
#define PAD_DRV_STRENGTH_5 (0x00000005 << 9)
|
||||
#define PAD_DRV_STRENGTH_6 (0x00000006 << 9)
|
||||
#define PAD_DRV_STRENGTH_7 (0x00000007 << 9)
|
||||
|
||||
static inline void PINMUX_Config_BL(uint32_t pin, uint32_t func) {
|
||||
volatile uint32_t *reg = &PERI_ON->GPIO_PINMUX_CTRL[pin >> 1];
|
||||
uint32_t shift = (pin & 1) << 4;
|
||||
uint32_t mask = 0xFFFF << shift;
|
||||
*reg = (*reg & ~mask) | (func << shift);
|
||||
}
|
||||
|
||||
static inline void PINMUX_Config(uint32_t pin, uint32_t func) {
|
||||
volatile uint32_t *reg = &PERI_ON->GPIO_PINMUX_CTRL[pin >> 1];
|
||||
if (pin & 1) {
|
||||
*reg = (*reg & 0x0000FFFF) | (func << 16);
|
||||
} else {
|
||||
*reg = (*reg & 0xFFFF0000) | func;
|
||||
}
|
||||
}
|
||||
|
||||
static inline void PINMUX_ConfigPadPull(uint8_t pin, uint8_t pull_type) {
|
||||
uint32_t reg_index = pin >> 1;
|
||||
uint32_t bit_pos = (pin & 1) << 4;
|
||||
uint32_t mask = 0xC0U << bit_pos;
|
||||
|
||||
PINMUX->PADCTR[reg_index] =
|
||||
(PINMUX->PADCTR[reg_index] & ~mask) | (pull_type << bit_pos);
|
||||
}
|
||||
|
||||
/* rtl8711b_gpio.h */
|
||||
|
||||
/* GPIO_Pull_parameter_definitions */
|
||||
#define GPIO_PuPd_NOPULL 0x00 // 00
|
||||
#define GPIO_PuPd_SHUTDOWN 0x00 // 00
|
||||
#define GPIO_PuPd_DOWN 0x80 // 10
|
||||
#define GPIO_PuPd_UP 0x40 // 01
|
||||
|
||||
/* GPIO_INT_Trigger_parameter_definitions */
|
||||
#define GPIO_INT_Trigger_LEVEL 0x0 /*This interrupt is level trigger */
|
||||
#define GPIO_INT_Trigger_EDGE 0x1 /*This interrupt is edge trigger */
|
||||
|
||||
#define IS_GPIOIT_LEVEL_TYPE(TYPE) \
|
||||
(((TYPE) == GPIO_INT_Trigger_LEVEL) || ((TYPE) == GPIO_INT_Trigger_EDGE))
|
||||
|
||||
/* GPIO_INT_Polarity_parameter_definitions */
|
||||
/*Setting interrupt to low active: falling edge or low level */
|
||||
#define GPIO_INT_POLARITY_ACTIVE_LOW 0x0
|
||||
/*Setting interrupt to high active: rising edge or high level */
|
||||
#define GPIO_INT_POLARITY_ACTIVE_HIGH 0x1
|
||||
|
||||
#define IS_GPIOIT_POLARITY_TYPE(TYPE) \
|
||||
(((TYPE) == GPIO_INT_POLARITY_ACTIVE_LOW) || \
|
||||
((TYPE) == GPIO_INT_POLARITY_ACTIVE_HIGH))
|
||||
|
||||
/* GPIO_INT_Debounce_parameter_definitions */
|
||||
#define GPIO_INT_DEBOUNCE_DISABLE 0x0 /*Disable interrupt debounce */
|
||||
#define GPIO_INT_DEBOUNCE_ENABLE 0x1 /*Enable interrupt debounce */
|
||||
|
||||
#define IS_GPIOIT_DEBOUNCE_TYPE(TYPE) \
|
||||
(((TYPE) == GPIO_INT_DEBOUNCE_DISABLE) || \
|
||||
((TYPE) == GPIO_INT_DEBOUNCE_ENABLE))
|
||||
|
||||
/* rtl8711b_rcc.h */
|
||||
|
||||
/* 0x230 REG_PESOC_CLK_CTRL */
|
||||
#define APBPeriph_GPIO_CLOCK (BIT_SOC_ACTCK_GPIO_EN)
|
||||
#define APBPeriph_GDMA1_CLOCK (BIT_SOC_ACTCK_GDMA1_EN)
|
||||
#define APBPeriph_GDMA0_CLOCK (BIT_SOC_ACTCK_GDMA0_EN)
|
||||
#define APBPeriph_GTIMER_CLOCK (BIT_SOC_ACTCK_TIMER_EN)
|
||||
#define APBPeriph_LOGUART_CLOCK (BIT_SOC_ACTCK_LOG_UART_EN)
|
||||
#define APBPeriph_FLASH_CLOCK (BIT_SOC_ACTCK_FLASH_EN)
|
||||
#define APBPeriph_VENDOR_REG_CLOCK (BIT_SOC_ACTCK_VENDOR_REG_EN)
|
||||
#define APBPeriph_TRACE_CLOCK (BIT_SOC_ACTCK_TRACE_EN)
|
||||
|
||||
/* 0x210 REG_SOC_FUNC_EN */
|
||||
#define APBPeriph_SECURITY_ENGINE BIT_SOC_SECURITY_ENGINE_EN
|
||||
#define APBPeriph_GTIMER BIT_SOC_GTIMER_EN
|
||||
#define APBPeriph_GDMA1 BIT_SOC_GDMA1_EN
|
||||
#define APBPeriph_GDMA0 BIT_SOC_GDMA0_EN
|
||||
#define APBPeriph_FLASH BIT_SOC_FLASH_EN
|
||||
#define APBPeriph_LXBUS BIT_SOC_LXBUS_EN
|
||||
|
||||
#endif
|
||||
Reference in New Issue
Block a user