mira/ch32v203-eth-node
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Mira
2024-10-10 02:40:12 +06:00
parent e56944bbcd
commit 8f1700c094
2 changed files with 129 additions and 16 deletions
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64
src/main.c
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@@ -24,10 +24,6 @@ void init_system(void) {
}
void init_gpio(void) {
// PA4 (CS)
GPIOA->CFGLR &= ~(0xf << (4 * 4));
GPIOA->CFGLR |= (GPIO_Speed_10MHz | GPIO_CNF_OUT_OD) << (4 * 4);
// GPIO PB3 pp
GPIOB->CFGLR &= ~(0xf << (4 * 3));
GPIOB->CFGLR |= (GPIO_Speed_10MHz | GPIO_CNF_OUT_PP) << (4 * 3);
@@ -41,27 +37,63 @@ void init_spi(void) {
// Enable SPI1
RCC->APB2PCENR |= RCC_APB2Periph_SPI1;
// PA5 (SCK) alternate function, push-pull
// CS on PA4, 10MHz Output, open-drain
GPIOA->CFGLR &= ~(0xf << (4 * 4));
GPIOA->CFGLR |= (GPIO_Speed_10MHz | GPIO_CNF_OUT_OD) << (4 * 4);
// SCK on PA5, 10MHz Output, alt func, push-pull
GPIOA->CFGLR &= ~(0xf << (4 * 5));
GPIOA->CFGLR |= (GPIO_Speed_50MHz | GPIO_CNF_OUT_PP_AF) << (4 * 5);
// PA6 (MISO) input, floating
// MOSI on PA7, 10MHz input, floating
GPIOA->CFGLR &= ~(0xf << (4 * 6));
GPIOA->CFGLR |= (GPIO_CNF_IN_FLOATING) << (4 * 6);
// PA7 (MOSI) alternate function, push-pull
// MISO on PA6, 10MHz Output, alt func, push-pull
GPIOA->CFGLR &= ~(0xf << (4 * 7));
GPIOA->CFGLR |= (GPIO_Speed_50MHz | GPIO_CNF_OUT_PP_AF) << (4 * 7);
SPI1->CTLR1 = SPI_Direction_2Lines_FullDuplex | SPI_Mode_Master |
SPI_DataSize_8b | SPI_CPOL_High | SPI_CPHA_2Edge | SPI_NSS_Soft |
SPI_BaudRatePrescaler_4 | SPI_FirstBit_MSB;
// SPI1->CTLR1 = (0 << 15) | // BIDIMODE
// (0 << 14) | // BIDIOE
// (0 << 13) | // CRCEN
// (0 << 12) | // CRCNEXT
// (0 << 11) | // DFF
// (0 << 10) | // RXONLY
// (1 << 9) | // SSM
// (0 << 8) | // SSI
// (0 << 7) | // LSBFIRST
// (0 << 6) | // SPE (Enable SPI)
// (1 << 5) | // BR[2] (Set baud rate)
// (0 << 4) | // BR[1]
// (0 << 3) | // BR[0]
// (1 << 2) | // MSTR (Master mode)
// (0 << 1) | // CPOL
// (0); // CPHA
SPI1->I2SCFGR &= SPI_Mode_Select; // Disable I2S mode
// SPI1->CRCR = 7; // 8-bit CRC polynomial
// SPI1->CTLR1 &= ~(SPI_CTLR1_DFF); // 8-bit data frame
SPI1->CTLR1 |= CTLR1_SPE_Set;
// reset control register
SPI1->CTLR1 = 0;
// CS high initially
GPIOA->BSHR = (1 << 4);
// set prescaler
// 001: FPCLK/4;
SPI1->CTLR1 = (SPI1->CTLR1 & ~SPI_CTLR1_BR) | (0x1 << 3);
// set clock polarity and phase
SPI1->CTLR1 |= (SPI_CPOL_Low | SPI_CPHA_1Edge);
// configure NSS pin, master mode
SPI1->CTLR1 |= SPI_NSS_Soft; // SSM NSS software control mode
// CH32V203 is master
SPI1->CTLR1 |= SPI_Mode_Master;
// set data direction and configure data pins
SPI1->CTLR1 |= SPI_Direction_2Lines_FullDuplex;
// disable I2S mode
SPI1->I2SCFGR &= SPI_Mode_Select;
SPI1->CTLR1 &= ~(SPI_CTLR1_DFF); // DFF 16bit data-length enable, writable
// only when SPE is 0
SPI1->CTLR1 |= SPI_CTLR1_SPE;
}
volatile int ip_assigned = 0;