kuwoyuki
8adc726b0b
Squashed commit of the following: commit 5f16309f629b9928d2134b85ae64af69bc3ebbcd Author: kuwoyuki <kuwoyuki@cock.li> Date: Sun Nov 24 22:55:15 2024 +0600 fix: Makefile, improve onewire retries commit 55496a3bda941b52ff349dc75c9c06eb5a37c07d Author: kuwoyuki <kuwoyuki@cock.li> Date: Mon Nov 18 00:41:18 2024 +0600 fix: make onewire validity less strict commit 3428a9bc9792508972ce3e7e4e35a64f047bca10 Author: kuwoyuki <kuwoyuki@cock.li> Date: Sun Nov 17 23:57:55 2024 +0600 chore: rm bins commit 1594e5ed430522b15466c8afa62ff7fb1b28947c Author: kuwoyuki <kuwoyuki@cock.li> Date: Sun Nov 17 23:32:01 2024 +0600 chore: unplatformiofy
132 lines
4.4 KiB
C
132 lines
4.4 KiB
C
#include "spi_dma.h"
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#include "ch32v003fun.h"
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#include "debug.h"
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#define RX_Channel DMA1_Channel2
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#define TX_Channel DMA1_Channel3
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static const uint8_t tx_dummy_byte = 0xFF;
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static uint8_t rx_dummy;
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void spi_select(void) {
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GPIOA->BCR = (1 << 4); // Set PA4 (CS) low
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}
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void spi_unselect(void) {
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GPIOA->BSHR = (1 << 4); // Set PA4 (CS) high
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}
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// SPI DMA
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void spidma_read_buffer(uint8_t* buf, uint16_t len) {
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// tx
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TX_Channel->MADDR = (uint32_t)&tx_dummy_byte;
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TX_Channel->CNTR = len;
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TX_Channel->CFGR &= ~DMA_MemoryInc_Enable;
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// rx
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RX_Channel->MADDR = (uint32_t)buf;
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RX_Channel->CNTR = len;
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RX_Channel->CFGR |= DMA_MemoryInc_Enable;
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// enable
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RX_Channel->CFGR |= DMA_CFGR1_EN;
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TX_Channel->CFGR |= DMA_CFGR1_EN;
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while (!(DMA1->INTFR & DMA1_FLAG_TC2) && !(DMA1->INTFR & DMA1_FLAG_TC3));
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/**
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* In transmission mode, when the DMA has written all the data to be
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* transmitted (flag TCIF is set in the DMA_ISR register), the BSY flag can be
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* monitored to ensure that the SPI communication is complete. This is
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* required to avoid corrupting the last transmission before disabling the SPI
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* or entering the Stop mode. The software must first wait until TXE=1 and
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* then until BSY=0.
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*/
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while (!(SPI1->STATR & SPI_STATR_TXE));
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while (SPI1->STATR & SPI_I2S_FLAG_BSY);
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// clear intfr
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DMA1->INTFCR |= DMA1_FLAG_TC2 | DMA1_FLAG_TC3;
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RX_Channel->CFGR &= ~DMA_CFGR1_EN;
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TX_Channel->CFGR &= ~DMA_CFGR1_EN;
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}
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void spidma_write_buffer(uint8_t* buf, uint16_t len) {
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// tx
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TX_Channel->MADDR = (uint32_t)buf;
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TX_Channel->CNTR = len;
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TX_Channel->CFGR |= DMA_MemoryInc_Enable;
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// rx
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RX_Channel->MADDR = (uint32_t)&rx_dummy;
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RX_Channel->CNTR = len;
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RX_Channel->CFGR &= ~DMA_MemoryInc_Enable;
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// enable
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TX_Channel->CFGR |= DMA_CFGR1_EN;
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RX_Channel->CFGR |= DMA_CFGR1_EN;
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while (!(DMA1->INTFR & DMA1_FLAG_TC2) && !(DMA1->INTFR & DMA1_FLAG_TC3));
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// wait for SPI to complete: TXE = 1, then BSY = 0
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while (!(SPI1->STATR & SPI_STATR_TXE));
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while (SPI1->STATR & SPI_I2S_FLAG_BSY);
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// clear intfr
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DMA1->INTFCR |= DMA1_FLAG_TC2 | DMA1_FLAG_TC3;
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RX_Channel->CFGR &= ~DMA_CFGR1_EN;
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TX_Channel->CFGR &= ~DMA_CFGR1_EN;
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}
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void spidma_init(void) {
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// Enable clock for GPIOA and SPI1
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RCC->APB2PCENR |= RCC_APB2Periph_GPIOA | RCC_APB2Periph_SPI1;
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// Enable clock for DMA1
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RCC->AHBPCENR |= RCC_AHBPeriph_DMA1;
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// SPI1 Pin Configuration
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// CS on PA4, 10MHz Output, push-pull
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GPIOA->CFGLR &= ~(0xf << (4 * 4));
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GPIOA->CFGLR |= (GPIO_Speed_10MHz | GPIO_CNF_OUT_PP) << (4 * 4);
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// SCK on PA5, 10MHz Output, alt func, push-pull
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GPIOA->CFGLR &= ~(0xf << (4 * 5));
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GPIOA->CFGLR |= (GPIO_Speed_50MHz | GPIO_CNF_OUT_PP_AF) << (4 * 5);
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// MISO on PA6, 10MHz input, floating
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GPIOA->CFGLR &= ~(0xf << (4 * 6));
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GPIOA->CFGLR |= (GPIO_CNF_IN_FLOATING) << (4 * 6);
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// MOSI on PA7, 10MHz Output, alt func, push-pull
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GPIOA->CFGLR &= ~(0xf << (4 * 7));
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GPIOA->CFGLR |= (GPIO_Speed_50MHz | GPIO_CNF_OUT_PP_AF) << (4 * 7);
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// Reset and Configure SPI1
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SPI1->CTLR1 = 0; // Clear CTLR1 initially
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SPI1->CTLR1 = SPI_Mode_Master | // Master mode
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SPI_Direction_2Lines_FullDuplex | // Full duplex
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SPI_DataSize_8b | // 8-bit data frame format
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SPI_CPHA_1Edge | // Clock polarity
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SPI_CPOL_Low | // Clock phase
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SPI_BaudRatePrescaler_64 | // Baud rate prescaler
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SPI_NSS_Soft; // Software NSS management
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// Enable TX and RX DMA
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SPI1->CTLR2 = SPI_CTLR2_TXDMAEN | SPI_CTLR2_RXDMAEN;
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SPI1->I2SCFGR &= SPI_Mode_Select; // Disable I2S mode
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SPI1->CTLR1 |= SPI_CTLR1_SPE; // Enable SPI
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// DMA setup
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TX_Channel->PADDR = (uint32_t)&SPI1->DATAR; // TX Channel
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TX_Channel->CFGR = DMA_M2M_Disable | DMA_Priority_VeryHigh |
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DMA_MemoryDataSize_Byte | DMA_PeripheralDataSize_Byte |
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DMA_MemoryInc_Enable | DMA_PeripheralInc_Disable |
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DMA_Mode_Normal | DMA_DIR_PeripheralDST;
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RX_Channel->PADDR = (uint32_t)&SPI1->DATAR; // RX Channel
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RX_Channel->CFGR = DMA_M2M_Disable | DMA_Priority_VeryHigh |
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DMA_MemoryDataSize_Byte | DMA_PeripheralDataSize_Byte |
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DMA_MemoryInc_Enable | DMA_PeripheralInc_Disable |
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DMA_Mode_Normal | DMA_DIR_PeripheralSRC;
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}
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