mira/ch32v208_sens
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fix: correctly deinit rcc before hse sw

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Mira
2025-11-10 12:00:21 +06:00
parent 6e29b34542
commit e448282aed
2 changed files with 12 additions and 4 deletions
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4
funconfig.h
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@@ -1,9 +1,9 @@
#ifndef _FUNCONFIG_H #ifndef _FUNCONFIG_H
#define _FUNCONFIG_H #define _FUNCONFIG_H
#define FUNCONF_USE_HSE 1 // #define FUNCONF_USE_HSE 1
#define FUNCONF_SYSTEM_CORE_CLOCK 120000000 #define FUNCONF_SYSTEM_CORE_CLOCK 120000000
#define FUNCONF_PLL_MULTIPLIER 15 // #define FUNCONF_PLL_MULTIPLIER 15
#define FUNCONF_SYSTICK_USE_HCLK 1 #define FUNCONF_SYSTICK_USE_HCLK 1
#endif #endif

12
main.c
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@@ -29,13 +29,21 @@
struct netif g_netif; struct netif g_netif;
static volatile int g_httpd_is_initialized = 0; static volatile int g_httpd_is_initialized = 0;
int clock_init(void);
void led_init(void); void led_init(void);
void lwip_stack_init(void); void lwip_stack_init(void);
static void set_sysclk_to_120mhz_from_hse(void) { static void set_sysclk_to_120mhz_from_hse(void) {
volatile uint32_t startup_counter = 0; uint32_t startup_counter = 0;
RCC->INTR = 0x009F0000; // clear PLL, CSSC, HSE, HSI and LSI ready flags.
// switch processor back to HSI so we don't eat dirt.
RCC->CFGR0 = 0;
// disable PLL so we can play with it.
RCC->CTLR &= ~RCC_PLLON;
// not sure why, need to reset here, otherwise PLLXTPRE is set.
RCC->CFGR0 = RCC_PLLSRC;
// enable HSE
RCC->CTLR |= RCC_HSEON; RCC->CTLR |= RCC_HSEON;
do { do {