234 lines
12 KiB
C
234 lines
12 KiB
C
#ifndef __ETHERNETIF_H
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#define __ETHERNETIF_H
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#include "lwip/err.h"
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#include "lwip/netif.h"
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void run_tx_test(void);
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void WritePHYReg(uint8_t reg_add, uint16_t reg_val);
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uint16_t ReadPHYReg(uint8_t reg_add);
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#define ROM_CFG_USERADR_ID 0x1FFFF7E8
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#define PHY_BMCR_FORCE_10BASE_T_HD ((uint16_t)0x0000)
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#define PHY_BMCR_FORCE_10BASE_T_FD ((uint16_t)0x0100) // 10M, Full Duplex
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#define PHY_ANAR_SELECTOR_FIELD 0x0001 // Selector for 802.3
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#define PHY_ANAR_10BASET_HD 0x0020 // 10M Half-Duplex
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#define PHY_ANAR_10BASET_FD 0x0040 // 10M Full-Duplex
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#define PHY_PHYSR 0x10 // PHY Status Register
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// Bits for CH32V20x PHYSR
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#define PHY_PHYSR_FULL_10M (1 << 2)
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#define PHY_BMCR_RESET ((uint16_t)0x8000) // Reset PHY
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#define PHY_BMCR_AN_ENABLE \
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((uint16_t)0x1000) // Enable Auto-Negotiation (Bit 12)
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#define PHY_BMCR_AN_RESTART \
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((uint16_t)0x0200) // Restart Auto-Negotiation (Bit 9)
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#define PHY_BMSR_LINK_STATUS (1 << 2)
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#define PHY_BMSR_AN_COMPLETE (1 << 5)
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#define PHY_MDIX_PN_MASK (3 << 2) // Mask for bits [3:2] -> 0x0C
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#define PHY_MDIX_PN_REVERSED \
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(1 << 2) // Value for reversed polarity (01b) -> 0x04
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/**
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DMA Tx Desciptor
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-----------------------------------------------------------------------------------------------
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TDES0 | OWN(31) | CTRL[30:26] | Reserved[25:24] | CTRL[23:20] |
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Reserved[19:17] | Status[16:0] |
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-----------------------------------------------------------------------------------------------
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TDES1 | Reserved[31:29] | Buffer2 ByteCount[28:16] | Reserved[15:13] | Buffer1
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ByteCount[12:0] |
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-----------------------------------------------------------------------------------------------
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TDES2 | Buffer1 Address [31:0] |
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-----------------------------------------------------------------------------------------------
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TDES3 | Buffer2 Address [31:0] / Next Desciptor Address
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[31:0] |
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------------------------------------------------------------------------------------------------
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*/
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/* Bit or field definition of TDES0 register (DMA Tx descriptor status
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* register)*/
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#define ETH_DMATxDesc_OWN \
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((uint32_t)0x80000000) /* OWN bit: descriptor is owned by DMA engine */
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#define ETH_DMATxDesc_IC ((uint32_t)0x40000000) /* Interrupt on Completion */
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#define ETH_DMATxDesc_LS ((uint32_t)0x20000000) /* Last Segment */
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#define ETH_DMATxDesc_FS ((uint32_t)0x10000000) /* First Segment */
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#define ETH_DMATxDesc_DC ((uint32_t)0x08000000) /* Disable CRC */
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#define ETH_DMATxDesc_DP ((uint32_t)0x04000000) /* Disable Padding */
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#define ETH_DMATxDesc_TTSE \
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((uint32_t)0x02000000) /* Transmit Time Stamp Enable */
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#define ETH_DMATxDesc_CIC \
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((uint32_t)0x00C00000) /* Checksum Insertion Control: 4 cases */
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#define ETH_DMATxDesc_CIC_ByPass \
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((uint32_t)0x00000000) /* Do Nothing: Checksum Engine is bypassed */
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#define ETH_DMATxDesc_CIC_IPV4Header \
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((uint32_t)0x00400000) /* IPV4 header Checksum Insertion */
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#define ETH_DMATxDesc_CIC_TCPUDPICMP_Segment \
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((uint32_t)0x00800000) /* TCP/UDP/ICMP Checksum Insertion calculated over \
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segment only */
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#define ETH_DMATxDesc_CIC_TCPUDPICMP_Full \
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((uint32_t)0x00C00000) /* TCP/UDP/ICMP Checksum Insertion fully calculated \
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*/
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#define ETH_DMATxDesc_TER ((uint32_t)0x00200000) /* Transmit End of Ring */
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#define ETH_DMATxDesc_TCH ((uint32_t)0x00100000) /* Second Address Chained */
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#define ETH_DMATxDesc_TTSS ((uint32_t)0x00020000) /* Tx Time Stamp Status */
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#define ETH_DMATxDesc_IHE ((uint32_t)0x00010000) /* IP Header Error */
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#define ETH_DMATxDesc_ES \
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((uint32_t)0x00008000) /* Error summary: OR of the following bits: UE || ED \
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|| EC || LCO || NC || LCA || FF || JT */
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#define ETH_DMATxDesc_JT ((uint32_t)0x00004000) /* Jabber Timeout */
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#define ETH_DMATxDesc_FF \
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((uint32_t)0x00002000) /* Frame Flushed: DMA/MTL flushed the frame due to SW \
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flush */
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#define ETH_DMATxDesc_PCE ((uint32_t)0x00001000) /* Payload Checksum Error */
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#define ETH_DMATxDesc_LCA \
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((uint32_t)0x00000800) /* Loss of Carrier: carrier lost during tramsmission \
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*/
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#define ETH_DMATxDesc_NC \
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((uint32_t)0x00000400) /* No Carrier: no carrier signal from the tranceiver \
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*/
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#define ETH_DMATxDesc_LCO \
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((uint32_t)0x00000200) /* Late Collision: transmission aborted due to \
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collision */
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#define ETH_DMATxDesc_EC \
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((uint32_t)0x00000100) /* Excessive Collision: transmission aborted after 16 \
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collisions */
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#define ETH_DMATxDesc_VF ((uint32_t)0x00000080) /* VLAN Frame */
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#define ETH_DMATxDesc_CC ((uint32_t)0x00000078) /* Collision Count */
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#define ETH_DMATxDesc_ED ((uint32_t)0x00000004) /* Excessive Deferral */
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#define ETH_DMATxDesc_UF \
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((uint32_t)0x00000002) /* Underflow Error: late data arrival from the memory \
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*/
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#define ETH_DMATxDesc_DB ((uint32_t)0x00000001) /* Deferred Bit */
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/* Field definition of TDES1 register */
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#define ETH_DMATxDesc_TBS2 ((uint32_t)0x1FFF0000) /* Transmit Buffer2 Size */
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#define ETH_DMATxDesc_TBS1 ((uint32_t)0x00001FFF) /* Transmit Buffer1 Size */
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/* Field definition of TDES2 register */
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#define ETH_DMATxDesc_B1AP ((uint32_t)0xFFFFFFFF) /* Buffer1 Address Pointer \
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*/
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/* Field definition of TDES3 register */
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#define ETH_DMATxDesc_B2AP ((uint32_t)0xFFFFFFFF) /* Buffer2 Address Pointer \
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*/
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/**
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DMA Rx Desciptor
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---------------------------------------------------------------------------------------------------------------------
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RDES0 | OWN(31) | Status [30:0] |
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---------------------------------------------------------------------------------------------------------------------
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RDES1 | CTRL(31) | Reserved[30:29] | Buffer2 ByteCount[28:16] | CTRL[15:14] |
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Reserved(13) | Buffer1 ByteCount[12:0] |
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---------------------------------------------------------------------------------------------------------------------
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RDES2 | Buffer1 Address [31:0] |
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---------------------------------------------------------------------------------------------------------------------
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RDES3 | Buffer2 Address [31:0] / Next Desciptor
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Address [31:0] |
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----------------------------------------------------------------------------------------------------------------------
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*/
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/* Bit or field definition of RDES0 register (DMA Rx descriptor status register)
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*/
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#define ETH_DMARxDesc_OWN \
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((uint32_t)0x80000000) /* OWN bit: descriptor is owned by DMA engine */
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#define ETH_DMARxDesc_AFM \
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((uint32_t)0x40000000) /* DA Filter Fail for the rx frame */
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#define ETH_DMARxDesc_FL \
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((uint32_t)0x3FFF0000) /* Receive descriptor frame length */
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#define ETH_DMARxDesc_ES \
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((uint32_t)0x00008000) /* Error summary: OR of the following bits: DE || OE \
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|| IPC || LC || RWT || RE || CE */
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#define ETH_DMARxDesc_DE \
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((uint32_t)0x00004000) /* Desciptor error: no more descriptors for receive \
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frame */
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#define ETH_DMARxDesc_SAF \
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((uint32_t)0x00002000) /* SA Filter Fail for the received frame */
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#define ETH_DMARxDesc_LE \
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((uint32_t)0x00001000) /* Frame size not matching with length field */
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#define ETH_DMARxDesc_OE \
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((uint32_t)0x00000800) /* Overflow Error: Frame was damaged due to buffer \
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overflow */
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#define ETH_DMARxDesc_VLAN \
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((uint32_t)0x00000400) /* VLAN Tag: received frame is a VLAN frame */
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#define ETH_DMARxDesc_FS \
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((uint32_t)0x00000200) /* First descriptor of the frame */
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#define ETH_DMARxDesc_LS \
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((uint32_t)0x00000100) /* Last descriptor of the frame */
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#define ETH_DMARxDesc_IPV4HCE \
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((uint32_t)0x00000080) /* IPC Checksum Error: Rx Ipv4 header checksum error \
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*/
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#define ETH_DMARxDesc_LC \
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((uint32_t)0x00000040) /* Late collision occurred during reception */
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#define ETH_DMARxDesc_FT \
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((uint32_t)0x00000020) /* Frame type - Ethernet, otherwise 802.3 */
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#define ETH_DMARxDesc_RWT \
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((uint32_t)0x00000010) /* Receive Watchdog Timeout: watchdog timer expired \
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during reception */
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#define ETH_DMARxDesc_RE \
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((uint32_t)0x00000008) /* Receive error: error reported by MII interface */
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#define ETH_DMARxDesc_DBE \
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((uint32_t)0x00000004) /* Dribble bit error: frame contains non int multiple \
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of 8 bits */
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#define ETH_DMARxDesc_CE ((uint32_t)0x00000002) /* CRC error */
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#define ETH_DMARxDesc_MAMPCE \
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((uint32_t)0x00000001) /* Rx MAC Address/Payload Checksum Error: Rx MAC \
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address matched/ Rx Payload Checksum Error */
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/* Bit or field definition of RDES1 register */
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#define ETH_DMARxDesc_DIC \
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((uint32_t)0x80000000) /* Disable Interrupt on Completion */
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#define ETH_DMARxDesc_RBS2 ((uint32_t)0x1FFF0000) /* Receive Buffer2 Size */
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#define ETH_DMARxDesc_RER ((uint32_t)0x00008000) /* Receive End of Ring */
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#define ETH_DMARxDesc_RCH ((uint32_t)0x00004000) /* Second Address Chained */
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#define ETH_DMARxDesc_RBS1 ((uint32_t)0x00001FFF) /* Receive Buffer1 Size */
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/* Field definition of RDES2 register */
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#define ETH_DMARxDesc_B1AP ((uint32_t)0xFFFFFFFF) /* Buffer1 Address Pointer \
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*/
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/* Field definition of RDES3 register */
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#define ETH_DMARxDesc_B2AP ((uint32_t)0xFFFFFFFF) /* Buffer2 Address Pointer \
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*/
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#define ETH_DMARxDesc_FrameLengthShift 16
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typedef struct {
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uint32_t volatile Status; /* Status */
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uint32_t ControlBufferSize; /* Control and Buffer1, Buffer2 lengths */
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uint32_t Buffer1Addr; /* Buffer1 address pointer */
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uint32_t Buffer2NextDescAddr; /* Buffer2 or next descriptor address pointer */
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} ETH_DMADESCTypeDef;
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/**
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* @brief Initialize the ethernet interface and lwIP network stack.
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* This function should be passed as the init function to netif_add().
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*
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* @param netif The lwIP network interface structure to be initialized.
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* @return ERR_OK if the loopif is initialized, ERR_MEM if private data couldn't
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* be allocated.
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*/
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err_t ethernetif_init(struct netif* netif);
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/**
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* @brief This function should be called periodically from your main loop
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* to check for incoming packets and pass them to lwIP.
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*
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* @param netif The lwIP network interface structure.
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*/
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void ethernetif_input(struct netif* netif);
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/**
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* @brief This function should be called periodically from your main loop
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* to check the link status and update lwIP accordingly.
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*
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* @param netif The lwIP network interface structure..
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*/
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void ethernetif_link_poll(struct netif* netif);
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#endif /* __ETHERNETIF_H */ |