mira/rtl8710bx-re
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

chore: wifi struct, systick

Browse Source
This commit is contained in:
Mira
2024-12-10 02:25:18 +06:00
parent c595663b78
commit f48c749e1b
5 changed files with 105 additions and 102 deletions
Download Patch File Download Diff File Expand all files Collapse all files

3
Makefile
View File

@@ -23,6 +23,7 @@ ASFLAGS = -mcpu=$(MCU) -mthumb -g
LDFLAGS = -T linker.ld -Map=$(BUILD_DIR)/$(PROJECT).map \
--gc-sections --no-warn-rwx-segments \
--defsym=_RAM_START_ADDR=$(RAM_START)
LIBFLAGS =
SRC_DIR = src
BUILD_DIR = build
@@ -60,7 +61,7 @@ $(BUILD_DIR)/%.o: $(SRC_DIR)/%.s
$(ELF): $(OBJS) $(ASM_OBJS)
@echo "LD $@"
@$(LD) $(LDFLAGS) -o $@ $^
@$(LD) $(LDFLAGS) -o $@ $^ $(LIBFLAGS)
$(BIN): $(ELF)
@echo "OBJCOPY $@"

164
include/rtl8710bx.h
View File

@@ -685,59 +685,38 @@ typedef struct {
} USOC_TypeDef;
/* 0x0000h ~ 0x00FFh System Configuration */
/* System Configuration: 0x0000h ~ 0x00FFh */
typedef struct {
__IO uint16_t ISO_CTRL; // 0x0000, 2 Byte
__IO uint16_t FUNC_EN; // 0x0002, 2 Byte
__IO uint32_t APS_FSMCO; // 0x0004, 4 Byte
__IO uint16_t CLKR; // 0x0008, 2 Byte
__IO uint16_t CR_9346; // 0x000A, 2 Byte
__IO uint16_t EE_VPD; // 0x000C, 2 Byte
__IO uint8_t AFE_MISC; // 0x0010, 1 Byte
__IO uint8_t SPS0_CTRL[7]; // 0x0011, 7 Byte
__IO uint32_t SPS_OCP_CFG; // 0x0018, 4 Byte
__IO uint8_t RSV_CTRL[3]; // 0x001C, 3 Byte
__IO uint8_t RF_CTRL; // 0x001F, 1 Byte
__IO uint8_t LPLDO_CTRL; // 0x0023, 1 Byte
__IO uint32_t AFE_XTAL_CTRL; // 0x0024, 4 Byte
__IO uint32_t AFE_PLL_CTRL; // 0x0028, 4 Byte
__IO uint32_t MAC_PLL_CTRL_EXT; // 0x002C, 4 Byte
__IO uint32_t EFUSE_CTRL; // 0x0030
__IO uint32_t EFUSE_TEST; // 0x0034
__IO uint32_t PWR_DATA; // 0x0038
__IO uint32_t CAL_TIMER; // 0x003C
__I uint16_t ACLK_MON; // 0x003E, Read-only
__IO uint16_t GPIO_MUXCFG; // 0x0040
__IO uint16_t GPIO_IO_SEL; // 0x0042
__IO uint8_t MAC_PINMUX_CFG; // 0x0043
__IO uint32_t GPIO_PIN_CTRL; // 0x0044
__IO uint32_t GPIO_INTM; // 0x0048
__IO uint8_t LEDCFG0; // 0x004C
__IO uint8_t LEDCFG1; // 0x004D
__IO uint8_t LEDCFG2; // 0x004E
__IO uint8_t LEDCFG3; // 0x004F
__IO uint32_t FSIMR; // 0x0050
__I uint32_t FSISR; // 0x0054, Status register
__IO uint32_t HSIMR; // 0x0058
__I uint32_t HSISR; // 0x005C, Status register
__IO uint32_t GPIO_EXT_CTRL; // 0x0060
__IO uint32_t MULTI_FUNC_CTRL; // 0x0068
__I uint32_t GPIO_STATUS; // 0x006C, Status register
__IO uint32_t SDIO_CTRL; // 0x0070
__IO uint32_t OPT_CTRL; // 0x0074
__IO uint32_t AFE_XTAL_CTRL_EXT; // 0x0078
__IO uint32_t MCUFWDL; // 0x0090
__I uint32_t BT_PATCH_STATUS; // 0x0088, Status register
__IO uint32_t HIMR0; // 0x00B0
__I uint32_t HISR0; // 0x00B4, Status register
__IO uint32_t HIMR1; // 0x00B8
__I uint32_t HISR1; // 0x00BC, Status register
__IO uint32_t PMC_DBG_CTRL2; // 0x00CC
__IO uint8_t EFUSE_BURN_GNT; // 0x00CF
__I uint32_t HPON_FSM; // 0x00EC, FSM state
__IO uint32_t SYS_CFG; // 0x00F0
__IO uint32_t SYS_CFG1; // 0x00FC
__I uint8_t ROM_VERSION; // 0x00FD, Read-only version
} WiFi_SYS_TypeDef;
__IO uint16_t SYS_ISO_CTRL; /* 0x0000, System power isolation ctrl */
__IO uint16_t WL_CLK_CTRL; /* 0x0002, WiFi clock gating and power ctrl */
__IO uint16_t SYS_FUNC_EN; /* 0x0004, System function blocks 1/0 */
__IO uint16_t RESERVED1; /* 0x0006 */
__IO uint16_t SYS_CLKR; /* 0x0008, System clock source sel */
__IO uint16_t RESERVED2[36]; /* 0x000A-0x004F */
__IO uint32_t AFE_CTRL; /* 0x0050, Analog front-end control settings? */
__IO uint32_t RESERVED3[2]; /* 0x0054-0x0058 */
__IO uint32_t WL_RF_PSS; /* 0x005C, RF power saving ctrl */
__IO uint32_t RESERVED4[3]; /* 0x0060-0x0068 */
__IO uint32_t EFUSE_INDIRECT_CTRL; /* 0x006C, eFuse indirect access control */
__IO uint32_t WL_PIN_FUNC_CTRL; /* 0x0070, WiFi GPIO func ctrl? */
__IO uint32_t RESERVED5[3]; /* 0x0074-0x007C */
__IO uint32_t HIMR0; /* 0x0080, Host interrupt mask register 0 */
__IO uint32_t HISR0; /* 0x0084, Host interrupt status flags 0 */
__IO uint32_t HCI_OPT_CTRL; /* 0x0088, Host controller interface opts */
__IO uint32_t RESERVED6; /* 0x008C */
__IO uint32_t FW_CTRL_V1; /* 0x0090, Firmware control and status */
__IO uint32_t RESERVED7[2]; /* 0x0094-0x0098 */
__IO uint32_t
USB_HOST_INDIRECT_DATA; /* 0x009C, USB host indirect access data */
__IO uint32_t RESERVED8[20]; /* 0x00A0-0x00EC */
__IO uint32_t EEPROM_CTRL; /* 0x00E0, EEPROM access control */
__IO uint32_t RESERVED9[3]; /* 0x00E4-0x00EC */
__IO uint32_t WL_STATUS; /* 0x00F0, WiFi subsystem status */
__IO uint32_t FW_DBG_STATUS; /* 0x00F4, Firmware debug info */
__IO uint32_t
USB_HOST_INDIRECT_ADDR; /* 0x00F8, USB host indirect access address */
__IO uint32_t SYS_CFG2; /* 0x00FC, REG_SYS_CFG2_8710B */
} WIFI_SYS_TypeDef;
/* 0x0100h ~ 0x01FFh MACTOP General Configuration */
typedef struct {
@@ -750,13 +729,15 @@ typedef struct {
__IO uint32_t TRXFF_BNDY; /* 0x0114 TRX FIFO Boundary */
__I uint32_t TRXFF_STATUS; /* 0x0118 TRX FIFO Status */
__I uint32_t RXFF_PTR; /* 0x011C RX FIFO Pointer */
uint8_t RESERVED2[0x12]; /* 0x0120-0x012E */
__IO uint8_t CPWM; /* 0x012F Control Power Management */
uint8_t RESERVED3[8]; /* 0x0130-0x0137 */
__IO uint32_t FTIMR; /* 0x0138 FW Timer Interrupt Mask Register */
uint8_t RESERVED4[4]; /* 0x013C-0x013F */
__IO uint16_t PKTBUF_DBG_CTRL; /* 0x0140 Packet Buffer Debug Control */
__IO uint16_t RXPKTBUF_CTRL; /* 0x0142 RX Packet Buffer Control */
uint8_t RESERVED2[12]; /* 0x0120-0x012B */
__IO uint8_t CPWM; /* 0x012C Control Power Management */
uint8_t RESERVED3[3]; /* 0x012D-0x012F */
__IO uint32_t FWIMR; /* 0x0130 FW Interrupt Mask Register */
__IO uint32_t FWISR; /* 0x0134 FW Interrupt Status Register */
__IO uint32_t FTIMR; /* 0x0138 FW Timer Interrupt Mask Register */
__IO uint32_t FTISR; /* 0x013C FW Timer Interrupt Status Register */
__IO uint16_t PKTBUF_DBG_CTRL; /* 0x0140 Packet Buffer Debug Control */
__IO uint16_t RXPKTBUF_CTRL; /* 0x0142 RX Packet Buffer Control */
__I uint32_t PKTBUF_DBG_DATA_L; /* 0x0144 Packet Buffer Debug Data Low */
__I uint32_t PKTBUF_DBG_DATA_H; /* 0x0148 Packet Buffer Debug Data High */
__IO uint32_t TC0_CTRL; /* 0x0150 TC0 Control Register */
@@ -788,7 +769,7 @@ typedef struct {
__IO uint32_t HMEBOX_EXT1; /* 0x01F4 Host Message Box Extension 1 */
__IO uint32_t HMEBOX_EXT2; /* 0x01F8 Host Message Box Extension 2 */
__IO uint32_t HMEBOX_EXT3; /* 0x01FC Host Message Box Extension 3 */
} WiFi_MAC_TypeDef;
} WIFI_MAC_TypeDef;
/* 0x0200h ~ 0x027Fh TXDMA Configuration */
typedef struct {
@@ -798,26 +779,26 @@ typedef struct {
__IO uint32_t TXDMA_OFFSET_CHK; /* 0x020C TX DMA Offset Check */
__I uint32_t TXDMA_STATUS; /* 0x0210 TX DMA Status */
__IO uint32_t RQPN_NPQ; /* 0x0214 Release Queue Page Number NPQ */
uint8_t RESERVED1[0x10]; /* 0x0218-0x0227 */
__IO uint32_t TDECTRL1; /* 0x0228 TX DMA Engine Control 1 */
uint8_t RESERVED2[0x54]; /* 0x022C-0x027F */
} WiFi_TXDMA_TypeDef;
uint8_t RESERVED1[12]; /* 0x0218-0x0223 */
__IO uint32_t AUTO_LLT; /* 0x0224 Auto LLT */
__IO uint32_t DWBCN1_CTRL; /* 0x0228 Beacon 1 TXDMA control? */
uint8_t RESERVED3[84]; /* 0x022C-0x027F */
} WIFI_TXDMA_TypeDef;
/* 0x0280h ~ 0x02FFh RXDMA Configuration */
typedef struct {
__IO uint32_t RXDMA_AGG_PG_TH; /* 0x0280 RX DMA Aggregation Page Threshold */
__IO uint32_t FW_UPD_RDPTR; /* 0x0284 Firmware Update Read Pointer */
__IO uint16_t RXDMA_CONTROL; /* 0x0286 RX DMA Control */
__IO uint8_t RXPKT_NUM; /* 0x0287 RX Packet Number */
__I uint32_t RXDMA_STATUS; /* 0x0288 RX DMA Status */
uint8_t RESERVED1[4]; /* 0x028C-0x028F */
__IO uint32_t RXDMA_PRO; /* 0x0290 RX DMA PRO */
uint8_t RESERVED2[0x28]; /* 0x0294-0x02BB */
__IO uint32_t AGG_PG_TH; /* 0x0280 RX DMA Aggregation Page Threshold */
__IO uint32_t RXPKT_NUM; /* 0x0284 The number of packets in RXPKTBUF */
__IO uint16_t RXDMA_CONTROL; /* 0x0286 Control the RX DMA */
uint8_t RESERVED1[1]; /* 0x0287 */
__IO uint32_t RXDMA_STATUS; /* 0x0288 RX DMA Status */
uint8_t RESERVED2[4]; /* 0x028C-0x028F */
__IO uint32_t RXDMA_MODE; /* 0x0290 RXDMA Mode */
uint8_t RESERVED3[0x28]; /* 0x0294-0x02BB */
__IO uint32_t EARLY_MODE_CONTROL; /* 0x02BC Early Mode Control */
uint8_t RESERVED3[0x30]; /* 0x02C0-0x02EF */
uint8_t RESERVED4[0x30]; /* 0x02C0-0x02EF */
__IO uint32_t RSVD5; /* 0x02F0 Reserved */
__IO uint32_t RSVD6; /* 0x02F4 Reserved */
uint8_t RESERVED4[8]; /* 0x02F8-0x02FF */
} WiFi_RXDMA_TypeDef;
uint8_t RESERVED5[0xC]; /* 0x02F4-0x02FF */
} WIFI_RXDMA_TypeDef;
/* 0x0300h ~ 0x03FFh LxBUS hal_com_reg.h */
/**
@@ -888,7 +869,7 @@ typedef struct {
/* Additional Control Registers */
__IO uint32_t INT_MASK; /* 0x03E8 - Interrupt Mask */
__I uint32_t INT_STATUS; /* 0x03EC - Interrupt Status */
} WiFi_LXBUS_TypeDef;
} WIFI_LXBUS_TypeDef;
/* 0x0400h ~ 0x047Fh Protocol Configuration */
typedef struct {
@@ -957,7 +938,7 @@ typedef struct {
__IO uint8_t RA_TRY_RATE_AGG_LMT; /* 0x04CF RA Try Rate Aggregation Limit */
__IO uint32_t MACID_PKT_DROP0; /* 0x04D0 MACID Packet Drop 0 */
uint8_t RESERVED[0x2C]; /* 0x04D4-0x04FF */
} WiFi_PROT_TypeDef;
} WIFI_PROT_TypeDef;
/* 0x0500h ~ 0x05FFh EDCA Configuration */
typedef struct {
@@ -1023,7 +1004,7 @@ typedef struct {
uint8_t RESERVED8[52]; /* 0x5C4-0x5F8 */
__IO uint32_t SCH_TXCMD; /* 0x05F8 Schedule TX command */
uint8_t RESERVED9[4]; /* 0x5FC-0x600 */
} WiFi_EDCA_TypeDef;
} WIFI_EDCA_TypeDef;
/* 0x0600h ~ 0x07FFh WMAC Configuration */
typedef struct {
@@ -1102,18 +1083,18 @@ typedef struct {
uint8_t RESERVED11[4]; /* 0x0710-0x0713 */
__IO uint32_t BFMEE_SEL; /* 0x0714 Beamformee Selection */
__IO uint32_t SND_PTCL_CTRL; /* 0x0718 Sound Protocol Control */
} WiFi_WMAC_TypeDef;
} WIFI_WMAC_TypeDef;
typedef struct {
WiFi_SYS_TypeDef SYS; /* 0x0000-0x00FF */
WiFi_MAC_TypeDef MAC; /* 0x0100-0x01FF */
WiFi_TXDMA_TypeDef TXDMA; /* 0x0200-0x027F */
WiFi_RXDMA_TypeDef RXDMA; /* 0x0280-0x02FF */
WiFi_LXBUS_TypeDef LXBUS; /* 0x0300-0x03FF */
WiFi_PROT_TypeDef PROT; /* 0x0400-0x047F */
WiFi_EDCA_TypeDef EDCA; /* 0x0500-0x05FF */
WiFi_WMAC_TypeDef WMAC; /* 0x0600-0x07FF */
} WiFi_TypeDef;
WIFI_SYS_TypeDef SYS; /* 0x0000-0x00FF */
WIFI_MAC_TypeDef MAC; /* 0x0100-0x01FF */
WIFI_TXDMA_TypeDef TXDMA; /* 0x0200-0x027F */
WIFI_RXDMA_TypeDef RXDMA; /* 0x0280-0x02FF */
WIFI_LXBUS_TypeDef LXBUS; /* 0x0300-0x03FF */
WIFI_PROT_TypeDef PROT; /* 0x0400-0x047F */
WIFI_EDCA_TypeDef EDCA; /* 0x0500-0x05FF */
WIFI_WMAC_TypeDef WMAC; /* 0x0600-0x07FF */
} WIFI_TypeDef;
/* Peripheral memory map */
#define SPI_FLASH_BASE 0x08000000
@@ -1191,7 +1172,7 @@ typedef struct {
#define TIM5 ((RTIM_TypeDef *)TIM5_BASE)
#define RTC ((RTC_TypeDef *)RTC_BASE)
#define IPSEC ((IPSEC_TypeDef *)CRYPTO_REG_BASE)
#define WIFI ((WiFi_TypeDef *)WIFI_REG_BASE)
#define WIFI ((WIFI_TypeDef *)WIFI_REG_BASE)
#define USOC ((USOC_TypeDef *)USOC_REG_BASE)
#define NCO32k ((NCO32k_TypeDef *)NCO1_REG_BASE)
#define NCO8M ((NCO8M_TypeDef *)NCO2_REG_BASE)
@@ -1222,7 +1203,8 @@ typedef struct {
/* Clock freq set macro */
#define SET_CPU_CLOCK(source) \
(SYSTEM_CTRL->CLK_CTRL1 = (SYSTEM_CTRL->CLK_CTRL1 & ~SYS_CLK_CPU_CLK_SEL) | (source))
(SYSTEM_CTRL->CLK_CTRL1 = \
(SYSTEM_CTRL->CLK_CTRL1 & ~SYS_CLK_CPU_CLK_SEL) | (source))
/* Clock sources - values pre-shifted to position */
#define CPU_CLK_125M (0 << CPU_CLK_POS)

12
include/systick.h Normal file
View File

@@ -0,0 +1,12 @@
#ifndef SYSTICK_H
#define SYSTICK_H
#include <stdint.h>
#define millis() (systick_millis)
extern volatile uint32_t systick_millis;
void Delay_Ms(uint32_t ms);
#endif

18
src/main.c
View File

@@ -4,27 +4,25 @@
#include "rom.h"
#include "rtl8710bx.h"
#include "system_rtl8710bx.h"
__attribute__((interrupt)) void SysTick_Handler(void) {
GPIOA->DR ^= (1 << 23);
}
#include "systick.h"
int main(void) {
printf("[main]\n");
printf("VTOR: 0x%08x\n", SCB->VTOR);
printf("SystemCoreClock: %d Hz\n", SystemCoreClock);
SET_CPU_CLOCK(CPU_CLK_62_5M);
SystemCoreClockUpdate();
printf("SystemCoreClock afer update: %d Hz\n", SystemCoreClock);
SysTick_Config(SystemCoreClock / 1000);
PERI_ON->SOC_PERI_FUNC1_EN |= BIT_PERI_GPIO_EN;
PERI_ON->PESOC_CLK_CTRL |= APBPeriph_GPIO_CLOCK;
PINMUX_Config(_PA_0, PINMUX_FN_GPIO, GPIO_PuPd_DOWN);
PINMUX_Config(_PA_23, PINMUX_FN_GPIO, GPIO_PuPd_NOPULL);
GPIOA->DDR |= (1 << 0) | (1 << 23);
// PINMUX_Config(_PA_23, PINMUX_FN_GPIO, GPIO_PuPd_NOPULL);
GPIOA->DDR |= (1 << 0);
uint32_t start_t = millis();
while (1) {
if ((millis() - start_t) > 1000) {
GPIOA->DR ^= (1 << 0);
start_t = millis();
}
}
}

10
src/systick.c Normal file
View File

@@ -0,0 +1,10 @@
#include "systick.h"
volatile uint32_t systick_millis;
__attribute__((interrupt)) void SysTick_Handler(void) { systick_millis++; }
void Delay_Ms(uint32_t ms) {
uint32_t start_ticks = millis();
while ((millis() - start_ticks) < ms);
}