chore: wifi struct, systick

Makefile

@@ -13,17 +13,17 @@ LD_FILE=linker.ld
 
 RAM_START := 0x10002000
 
-CFLAGS = -mcpu=$(MCU) -mthumb \
+CFLAGS = -mcpu=$(MCU) -mthumb -mfloat-abi=hard -mgeneral-regs-only -lm \
     -Wall -Wextra -g3 \
     -Os -ffunction-sections -fdata-sections \
-    -nostartfiles -Wl,-T,$(LD_FILE) -u main -Wl,--gc-sections \
+    -nostartfiles -Wl,-T,$(LD_FILE) -u main -Wl,--gc-sections
-    -DLOAD_ADDRESS=$(LOAD_ADDRESS)
 
 ASFLAGS = -mcpu=$(MCU) -mthumb -g
 
 LDFLAGS = -T linker.ld -Map=$(BUILD_DIR)/$(PROJECT).map \
     --gc-sections --no-warn-rwx-segments \
     --defsym=_RAM_START_ADDR=$(RAM_START)
+LIBFLAGS = 
 
 SRC_DIR = src
 BUILD_DIR = build
@@ -61,7 +61,7 @@ $(BUILD_DIR)/%.o: $(SRC_DIR)/%.s
 
 $(ELF): $(OBJS) $(ASM_OBJS)
 	@echo "LD $@"
-	@$(LD) $(LDFLAGS) -o $@ $^
+	@$(LD) $(LDFLAGS) -o $@ $^ $(LIBFLAGS)
 
 $(BIN): $(ELF)
 	@echo "OBJCOPY $@"

docs/wifi.md

@@ -128,6 +128,152 @@ $ find . -type f -name "*.o" -exec bash -c '
 ./lib_wlan/rtl8711b_phycfg.o:          U ROM_odm_SetCrystalCap
 ```
 
+### DMA
+
+```c
+// 0x40080000
+typedef struct {
+    // 0x000-0x1FF: MAC/BB control registers
+    uint32_t reserved1[...];     // 0x000-0x0FC
+    __IO uint32_t NET_TYPE;     // 0x100 - bits [17:16] = network type
+    __IO uint8_t TRANSFER_PAGE_SIZE; // 0x104 - Transfer page size
+    uint8_t reserved[...];          // Fill to 0x108
+    __IO uint16_t REG_PRIORITY;      // 0x10C - Priority configuration
+    uint32_t reserved[...];
+    __IO uint16_t PAGE_BOUNDARY;  // 0x116 - Page Boundary config, set to 0x3F7F
+    uint32_t reserved[...];  // Continue to 0x200
+
+    // 0x200-0x2FF: System control/status
+    uint32_t reserved[...];                  // 0x200-0x207
+    __IO uint8_t TX_BUFFER_BOUNDARY2;       // 0x209
+    uint8_t reserved[...];                 // 0x20A-0x20B
+    __IO uint32_t REG_20C;                  // 0x20C - DMA Global Enable (bit 28)
+    uint8_t reserved[...];                // 0x210-0x223
+    __IO uint32_t REG_224;                  // 0x224 - LLT Status (bit 16 = busy)
+    uint8_t reserved[...];                 // 0x225-0x228
+    __IO uint8_t TX_BUFFER_BOUNDARY3;       // 0x229
+    __IO uint8_t REG_22A;                   // 0x22A - sets bit 1 if a2 true
+    uint32_t reserved[52];               // -> 0x2FF
+
+    // 0x300-0x3FF: DMA & Queue
+    __IO uint32_t DMA_CTRL;     // 0x300
+    __IO uint32_t reserved3;
+    __IO uint32_t QUEUE4;       // 0x308
+    __IO uint32_t reserved4;
+    __IO uint32_t QUEUE5;       // 0x310
+    __IO uint32_t reserved5;
+    __IO uint32_t TX_BASE;      // 0x318
+    __IO uint32_t reserved6;
+    __IO uint32_t QUEUE1;       // 0x320
+    __IO uint32_t reserved7;
+    __IO uint32_t QUEUE2;       // 0x328
+    __IO uint32_t reserved8;
+    __IO uint32_t QUEUE3;       // 0x330
+    __IO uint32_t reserved9;
+    __IO uint32_t RX_QUEUE;     // 0x338
+    __IO uint32_t QUEUE6;       // 0x340
+    uint32_t reserved[...];
+    __IO uint16_t Q_CFG[14];    // 0x380-0x39A
+    uint16_t reserved11;
+    uint32_t reserved[...];
+    __IO uint32_t DMA_MASK;     // 0x3E8
+    uint32_t reserved[...];
+
+    // 0x400-0x4FF region
+    uint32_t reserved[...];              // 0x400-0x420
+    __IO uint8_t TX_BUFFER_BOUNDARY4;   // 0x424
+    __IO uint8_t TX_BUFFER_BOUNDARY5;   // 0x425
+    __IO uint16_t ADAPT_CTRL1;       // 0x428 - a2 in both bytes or first SIFS timing? 4106
+   __IO uint16_t ADAPT_CTRL2;       // 0x42A - (a3 & 0x3F) in both bytes
+   uint32_t reserved[4];         // 0x42C-0x43C
+   __IO uint32_t ADAPT_CTRL3;       // 0x440 - a1 | (old[31:20] << 20)
+    uint32_t reserved[...];           // 0x444-0x456
+    __IO uint8_t TX_BUFFER_BOUNDARY6;   // 0x457
+    uint32_t reserved4_2;               // 0x458-0x45B
+    __IO uint8_t MODE_CTRL2;            // 0x45C - Controlled by a2 parameter (80 or 0)
+    __IO uint8_t TX_BUFFER_BOUNDARY7;   // 0x45D (same as BOUND7), InitTxBufferBoundary
+    uint8_t reserved[...]; 
+   __IO uint16_t SIFS3;             // 0x514 - Third SIFS timing  
+   __IO uint16_t SIFS4;             // 0x516 - Fourth SIFS timing
+
+    // 0x600-0x6FF region
+    uint8_t reserved[...];               // 0x600-0x60E
+    __IO uint8_t DRIVER_INFO_SIZE;   // 0x60F - Driver info size
+     __IO uint16_t SIFS2;             // 0x63A - Second SIFS timing
+} WIFI_TypeDef;
+
+// TX Ring
+typedef struct {
+    uint32_t base_addr;         // TX_BASE
+    uint32_t reserved1[7];      // 28b
+    uint32_t queue1;            // QUEUE1
+    uint32_t reserved2[7];
+    uint32_t queue2;            // QUEUE2
+    uint32_t reserved3[7];
+    uint32_t queue3;            // QUEUE3
+    uint32_t reserved4[7];
+    uint32_t queue4;            // QUEUE4
+    uint32_t reserved5[7];
+    uint32_t queue5;            // QUEUE5
+    uint32_t reserved6[7];
+    uint32_t queue6;            // QUEUE6
+    uint32_t reserved7[7];
+} TX_RING_TypeDef;
+
+// RX Ring
+typedef struct {
+    uint32_t base_addr;         // RX_QUEUE
+    uint32_t reserved[7];       // ?
+} RX_RING_TypeDef;
+```
+
+```c
+// wireless modes from cur_wireless_mode mapping
+typedef enum {
+    WIRELESS_MODE_2 = 2,    // First valid value (v2 starts from 0)
+    // ... up to WIRELESS_MODE_16, v2 > 0xE check
+} WIRELESS_MODE;
+
+// HalData[60] seems to be some hardware capability/mode that affects a2
+typedef struct _ADAPTER {
+    uint8_t *HalData;           // HalData[60] determines MODE_CTRL2 value
+    struct {
+        uint8_t cur_wireless_mode;  // current wireless mode
+    } mlmeextpriv;
+    // ... other fields
+} ADAPTER, *PADAPTER;
+```
+
+```c
+// Network type values (2-bit field)
+#define NET_TYPE_MASK    (3 << 16)     // 0x00030000
+#define NET_TYPE_SHIFT   16
+
+// REG_PRIORITY bit fields
+#define PRIO_1_MASK     (0x3 << 8)    // a1 & 3
+#define PRIO_2_MASK     (0x3 << 10)   // a2 & 3
+#define PRIO_3_MASK     (0x3 << 12)   // a5 & 3
+#define PRIO_4_MASK     (0x3 << 4)    // a4 & 3
+#define PRIO_5_MASK     (0x3 << 6)    // a3 << 6
+#define PRIO_6_MASK     (0x3 << 14)   // a6 << 14
+#define PRIO_BASE_MASK  0x7           // preserved bits
+// Called with (1,1,2,3,3,3)
+// Would set bits:
+// [15:14] = 3 (a6)
+// [13:12] = 3 (a5)
+// [11:10] = 1 (a2)
+// [9:8]   = 1 (a1)
+// [7:6]   = 2 (a3)
+// [5:4]   = 3 (a4)
+// [2:0]   = preserved
+
+// ADAPT_CTRL
+// Called with (1048561, 16, 48)
+// ADAPT_CTRL1 = 0x1010  (16 | (16 << 8))
+// ADAPT_CTRL2 = 0x3030  ((48 & 0x3F) | ((48 & 0x3F) << 8))
+// ADAPT_CTRL3 preserves top 12 bits, lower 20 from 1048561
+```
+
 ```mermaid
 sequenceDiagram
     participant Device

docs/wifi_mem_map.py

@@ -0,0 +1,29 @@
+from ida_segment import *
+from ida_bytes import *
+from idc import *
+
+
+def setup_wifi_regions():
+    WIFI_BASE = 0x40080000
+    SIE_BASE = 0x400C0000
+
+    WIFI_SIZE = SIE_BASE - WIFI_BASE
+    SIE_SIZE = 0x1000
+
+    print("Setting up WiFi memory regions...")
+
+    if not add_segm(0, WIFI_BASE, SIE_BASE, "WIFI", "DATA"):
+        print("Failed to create WIFI segment")
+        return
+
+    if not add_segm(0, SIE_BASE, SIE_BASE + SIE_SIZE, "SIE", "DATA"):
+        print("Failed to create SIE segment")
+        return
+
+    print(f"Memory regions created:")
+    print(f"WIFI: {hex(WIFI_BASE)} - {hex(SIE_BASE-1)}")
+    print(f"SIE:  {hex(SIE_BASE)} - {hex(SIE_BASE + SIE_SIZE-1)}")
+
+
+if __name__ == "__main__":
+    setup_wifi_regions()

include/odm_stuff.h

@@ -0,0 +1,189 @@
+
+/* @2 RF REG LIST */
+#define ODM_REG_RF_MODE_11N 0x00
+#define ODM_REG_RF_0B_11N 0x0B
+#define ODM_REG_CHNBW_11N 0x18
+#define ODM_REG_RF_1D_11N 0x1D
+#define ODM_REG_T_METER_11N 0x24
+#define ODM_REG_RF_25_11N 0x25
+#define ODM_REG_RF_26_11N 0x26
+#define ODM_REG_RF_27_11N 0x27
+#define ODM_REG_RF_2B_11N 0x2B
+#define ODM_REG_RF_2C_11N 0x2C
+#define ODM_REG_RXRF_A3_11N 0x3C
+#define ODM_REG_T_METER_92D_11N 0x42
+#define ODM_REG_T_METER_88E_11N 0x42
+#define ODM_REF_RF_DF_11N 0xDF
+
+/* @2 BB REG LIST
+ * PAGE 8
+ */
+#define ODM_REG_BB_CTRL_11N 0x800
+#define ODM_REG_RF_PIN_11N 0x804
+#define ODM_REG_PSD_CTRL_11N 0x808
+#define ODM_REG_TX_ANT_CTRL_11N 0x80C
+#define ODM_REG_BB_PWR_SAV5_11N 0x818
+#define ODM_REG_CCK_RPT_FORMAT_11N 0x824
+#define ODM_REG_CCK_RPT_FORMAT_11N_B 0x82C
+#define ODM_REG_RX_DEFAULT_A_11N 0x858
+#define ODM_REG_RX_DEFAULT_B_11N 0x85A
+#define ODM_REG_BB_PWR_SAV3_11N 0x85C
+#define ODM_REG_ANTSEL_CTRL_11N 0x860
+#define ODM_REG_RX_ANT_CTRL_11N 0x864
+#define ODM_REG_PIN_CTRL_11N 0x870
+#define ODM_REG_BB_PWR_SAV1_11N 0x874
+#define ODM_REG_ANTSEL_PATH_11N 0x878
+#define ODM_REG_BB_3WIRE_11N 0x88C
+#define ODM_REG_SC_CNT_11N 0x8C4
+#define ODM_REG_PSD_DATA_11N 0x8B4
+#define ODM_REG_CCX_PERIOD_11N 0x894
+#define ODM_REG_NHM_TH9_TH10_11N 0x890
+#define ODM_REG_CLM_11N 0x890
+#define ODM_REG_NHM_TH3_TO_TH0_11N 0x898
+#define ODM_REG_NHM_TH7_TO_TH4_11N 0x89c
+#define ODM_REG_NHM_TH8_11N 0xe28
+#define ODM_REG_CLM_READY_11N 0x8b4
+#define ODM_REG_CLM_RESULT_11N 0x8d0
+#define ODM_REG_NHM_CNT_11N 0x8d8
+
+/* @For struct acs_info, Jeffery, 2014-12-26 */
+#define ODM_REG_NHM_CNT7_TO_CNT4_11N 0x8dc
+#define ODM_REG_NHM_CNT9_TO_CNT8_11N 0x8d0
+#define ODM_REG_NHM_CNT10_TO_CNT11_11N 0x8d4
+
+/* PAGE 9 */
+#define ODM_REG_BB_CTRL_PAGE9_11N 0x900
+#define ODM_REG_DBG_RPT_11N 0x908
+#define ODM_REG_BB_TX_PATH_11N 0x90c
+#define ODM_REG_ANT_MAPPING1_11N 0x914
+#define ODM_REG_ANT_MAPPING2_11N 0x918
+#define ODM_REG_EDCCA_DOWN_OPT_11N 0x948
+#define ODM_REG_RX_DFIR_MOD_97F 0x948
+#define ODM_REG_SOML_97F 0x998
+
+/* PAGE A */
+#define ODM_REG_CCK_ANTDIV_PARA1_11N 0xA00
+#define ODM_REG_CCK_ANT_SEL_11N 0xA04
+#define ODM_REG_CCK_CCA_11N 0xA0A
+#define ODM_REG_CCK_ANTDIV_PARA2_11N 0xA0C
+#define ODM_REG_CCK_ANTDIV_PARA3_11N 0xA10
+#define ODM_REG_CCK_ANTDIV_PARA4_11N 0xA14
+#define ODM_REG_CCK_FILTER_PARA1_11N 0xA22
+#define ODM_REG_CCK_FILTER_PARA2_11N 0xA23
+#define ODM_REG_CCK_FILTER_PARA3_11N 0xA24
+#define ODM_REG_CCK_FILTER_PARA4_11N 0xA25
+#define ODM_REG_CCK_FILTER_PARA5_11N 0xA26
+#define ODM_REG_CCK_FILTER_PARA6_11N 0xA27
+#define ODM_REG_CCK_FILTER_PARA7_11N 0xA28
+#define ODM_REG_CCK_FILTER_PARA8_11N 0xA29
+#define ODM_REG_CCK_FA_RST_11N 0xA2C
+#define ODM_REG_CCK_FA_MSB_11N 0xA58
+#define ODM_REG_CCK_FA_LSB_11N 0xA5C
+#define ODM_REG_CCK_CCA_CNT_11N 0xA60
+#define ODM_REG_BB_PWR_SAV4_11N 0xA74
+/* PAGE B */
+#define ODM_REG_LNA_SWITCH_11N 0xB2C
+#define ODM_REG_PATH_SWITCH_11N 0xB30
+#define ODM_REG_RSSI_CTRL_11N 0xB38
+#define ODM_REG_CONFIG_ANTA_11N 0xB68
+#define ODM_REG_RSSI_BT_11N 0xB9C
+#define ODM_REG_RXCK_RFMOD 0xBB0
+#define ODM_REG_EDCCA_DCNF_97F 0xBC0
+
+/* PAGE C */
+#define ODM_REG_OFDM_FA_HOLDC_11N 0xC00
+#define ODM_REG_BB_RX_PATH_11N 0xC04
+#define ODM_REG_TRMUX_11N 0xC08
+#define ODM_REG_OFDM_FA_RSTC_11N 0xC0C
+#define ODM_REG_DOWNSAM_FACTOR_11N 0xC10
+#define ODM_REG_RXIQI_MATRIX_11N 0xC14
+#define ODM_REG_TXIQK_MATRIX_LSB1_11N 0xC4C
+#define ODM_REG_IGI_A_11N 0xC50
+#define ODM_REG_ANTDIV_PARA2_11N 0xC54
+#define ODM_REG_IGI_B_11N 0xC58
+#define ODM_REG_ANTDIV_PARA3_11N 0xC5C
+#define ODM_REG_L1SBD_PD_CH_11N 0XC6C
+#define ODM_REG_BB_PWR_SAV2_11N 0xC70
+#define ODM_REG_BB_AGC_SET_2_11N 0xc74
+#define ODM_REG_RX_OFF_11N 0xC7C
+#define ODM_REG_TXIQK_MATRIXA_11N 0xC80
+#define ODM_REG_TXIQK_MATRIXB_11N 0xC88
+#define ODM_REG_TXIQK_MATRIXA_LSB2_11N 0xC94
+#define ODM_REG_TXIQK_MATRIXB_LSB2_11N 0xC9C
+#define ODM_REG_RXIQK_MATRIX_LSB_11N 0xCA0
+#define ODM_REG_ANTDIV_PARA1_11N 0xCA4
+#define ODM_REG_SMALL_BANDWIDTH_11N 0xCE4
+#define ODM_REG_OFDM_FA_TYPE1_11N 0xCF0
+/* PAGE D */
+#define ODM_REG_OFDM_FA_RSTD_11N 0xD00
+#define ODM_REG_BB_RX_ANT_11N 0xD04
+#define ODM_REG_BB_ATC_11N 0xD2C
+#define ODM_REG_OFDM_FA_TYPE2_11N 0xDA0
+#define ODM_REG_OFDM_FA_TYPE3_11N 0xDA4
+#define ODM_REG_OFDM_FA_TYPE4_11N 0xDA8
+#define ODM_REG_RPT_11N 0xDF4
+/* PAGE E */
+#define ODM_REG_TXAGC_A_6_18_11N 0xE00
+#define ODM_REG_TXAGC_A_24_54_11N 0xE04
+#define ODM_REG_TXAGC_A_1_MCS32_11N 0xE08
+#define ODM_REG_TXAGC_A_MCS0_3_11N 0xE10
+#define ODM_REG_TXAGC_A_MCS4_7_11N 0xE14
+#define ODM_REG_TXAGC_A_MCS8_11_11N 0xE18
+#define ODM_REG_TXAGC_A_MCS12_15_11N 0xE1C
+#define ODM_REG_EDCCA_DCNF_11N 0xE24
+#define ODM_REG_TAP_UPD_97F 0xE24
+#define ODM_REG_FPGA0_IQK_11N 0xE28
+#define ODM_REG_PAGE_B1_97F 0xE28
+#define ODM_REG_TXIQK_TONE_A_11N 0xE30
+#define ODM_REG_RXIQK_TONE_A_11N 0xE34
+#define ODM_REG_TXIQK_PI_A_11N 0xE38
+#define ODM_REG_RXIQK_PI_A_11N 0xE3C
+#define ODM_REG_TXIQK_11N 0xE40
+#define ODM_REG_RXIQK_11N 0xE44
+#define ODM_REG_IQK_AGC_PTS_11N 0xE48
+#define ODM_REG_IQK_AGC_RSP_11N 0xE4C
+#define ODM_REG_BLUETOOTH_11N 0xE6C
+#define ODM_REG_RX_WAIT_CCA_11N 0xE70
+#define ODM_REG_TX_CCK_RFON_11N 0xE74
+#define ODM_REG_TX_CCK_BBON_11N 0xE78
+#define ODM_REG_OFDM_RFON_11N 0xE7C
+#define ODM_REG_OFDM_BBON_11N 0xE80
+#define ODM_REG_TX2RX_11N 0xE84
+#define ODM_REG_TX2TX_11N 0xE88
+#define ODM_REG_RX_CCK_11N 0xE8C
+#define ODM_REG_RX_OFDM_11N 0xED0
+#define ODM_REG_RX_WAIT_RIFS_11N 0xED4
+#define ODM_REG_RX2RX_11N 0xED8
+#define ODM_REG_STANDBY_11N 0xEDC
+#define ODM_REG_SLEEP_11N 0xEE0
+#define ODM_REG_PMPD_ANAEN_11N 0xEEC
+/* PAGE F */
+#define ODM_REG_PAGE_F_RST_11N 0xF14
+#define ODM_REG_IGI_C_11N 0xF84
+#define ODM_REG_IGI_D_11N 0xF88
+#define ODM_REG_CCK_CRC32_ERROR_CNT_11N 0xF84
+#define ODM_REG_CCK_CRC32_OK_CNT_11N 0xF88
+#define ODM_REG_HT_CRC32_CNT_11N 0xF90
+#define ODM_REG_OFDM_CRC32_CNT_11N 0xF94
+#define ODM_REG_HT_CRC32_CNT_11N_AGG 0xFB8
+
+/* @2 MAC REG LIST */
+#define ODM_REG_BB_RST_11N 0x02
+#define ODM_REG_ANTSEL_PIN_11N 0x4C
+#define ODM_REG_EARLY_MODE_11N 0x4D0
+#define ODM_REG_RSSI_MONITOR_11N 0x4FE
+#define ODM_REG_EDCA_VO_11N 0x500
+#define ODM_REG_EDCA_VI_11N 0x504
+#define ODM_REG_EDCA_BE_11N 0x508
+#define ODM_REG_EDCA_BK_11N 0x50C
+#define ODM_REG_TXPAUSE_11N 0x522
+#define ODM_REG_RESP_TX_11N 0x6D8
+#define ODM_REG_ANT_TRAIN_PARA1_11N 0x7b0
+#define ODM_REG_ANT_TRAIN_PARA2_11N 0x7b4
+
+/* @DIG Related */
+#define ODM_BIT_IGI_11N 0x0000007F
+#define ODM_BIT_CCK_RPT_FORMAT_11N BIT(9)
+#define ODM_BIT_BB_RX_PATH_11N 0xF
+#define ODM_BIT_BB_TX_PATH_11N 0xF
+#define ODM_BIT_BB_ATC_11N BIT(11)

include/rom.h

@@ -0,0 +1,11 @@
+#ifndef ROM_H
+#define ROM_H
+
+#include <stdint.h>
+
+extern uint32_t DiagPrintf(const char *fmt, ...)
+    __attribute__((format(printf, 1, 2)));
+
+#define printf DiagPrintf
+
+#endif  // ROM_H

include/system_rtl8710bx.h

@@ -0,0 +1,52 @@
+#ifndef SYSTEM_RTL8710BX
+#define SYSTEM_RTL8710BX
+
+#include <stdint.h>
+
+// #define USE_ROM_TABLES
+
+#ifdef USE_ROM_TABLES
+#define CPU_CLK_TABLE_ADDR 0x00046E68
+#define XTAL_TABLE_ADDR 0x00046E10
+/* for init inline asm */
+#define CPU_CLK_TABLE ((const uint32_t*)CPU_CLK_TABLE_ADDR)
+#define XTAL_TABLE ((const uint32_t*)XTAL_TABLE_ADDR)
+#else
+
+/* CPU clock frequency table (Hz) */
+static const uint32_t CPU_CLK_TABLE[] = {
+    125000000, /* 125 MHz */
+    62500000,  /* 62.5 MHz */
+    31250000,  /* 31.25 MHz */
+    15625000,  /* 15.625 MHz */
+    7812500,   /* 7.8125 MHz */
+    4000000    /* 4 MHz */
+};
+
+/* Crystal oscillator frequency table (Hz) */
+static const uint32_t XTAL_TABLE[] = {
+    40000000, /* 40 MHz */
+    25000000, /* 25 MHz */
+    13000000, /* 13 MHz */
+    19200000, /* 19.2 MHz */
+    20000000, /* 20 MHz */
+    26000000, /* 26 MHz */
+    38400000, /* 38.4 MHz */
+    17664000, /* 17.664 MHz */
+    16000000, /* 16 MHz */
+    14318000, /* 14.318 MHz */
+    12000000, /* 12 MHz */
+};
+/* for init inline asm */
+#define CPU_CLK_TABLE_ADDR ((uint32_t)CPU_CLK_TABLE)
+#define XTAL_TABLE_ADDR ((uint32_t)XTAL_TABLE)
+
+#endif
+
+/* System Clock Frequency (Core Clock)*/
+extern uint32_t SystemCoreClock;
+
+void SystemCoreClockUpdate(void);
+void SystemInit(void);
+
+#endif  // SYSTEM_RTL8710BX

include/systick.h

@@ -0,0 +1,12 @@
+#ifndef SYSTICK_H
+#define SYSTICK_H
+
+#include <stdint.h>
+
+#define millis() (systick_millis)
+
+extern volatile uint32_t systick_millis;
+
+void Delay_Ms(uint32_t ms);
+
+#endif

linker.ld

@@ -24,10 +24,16 @@ SECTIONS
         . = ALIGN(4);
         . += 20; 
         LONG(_init + 1)
-        LONG(0x88167923) /* ROM checks this @ 0x10002018 */
+        /* even though we can supposedly tell the ROM where to copy us to
-        . = ALIGN(8);
+         * it will still check for this signature at 0x10002018... */
+        LONG(0x88167923) 
+        . = ALIGN(128);
+        _real_vector_table = .;
         *(.vectors)
-        *(.text* .rodata* .data*)
+        . = ALIGN(4);
+        *(.text*)
+        *(.rodata*)
+        *(.data*)
     }
 
     .bss : {

src/boot.s

@@ -1,31 +1,16 @@
 .syntax unified
 .cpu cortex-m4
 
-.section .text
-.thumb_func
-_startup:
-    /* zero .bss section */
-    ldr r0, =_bss_start
-    ldr r1, =_bss_end
-    movs r2, #0
-1:  cmp r0, r1
-    itt lt
-    strlt r2, [r0], #4
-    blt 1b
-2:
-    bl main
-1:  b 1b
-
-.section .text
 .global _init
 /* cold boot from ROM */
 _init:
+    cpsid i
     ldr sp, =_stack_top
     ldr r0, =_vector_table
     ldr r1, =0xE000ED08
     str r0, [r1]
 
-    b _startup
+    b SystemInit
 
 .section .vectors
 .global _vector_table
@@ -253,10 +238,8 @@ Default_Handler:
 
 /* Reset_Handler will be global */
 .global Reset_Handler
-
-.section .text
 .thumb_func
 Reset_Handler:
-    b _startup
+    b SystemInit
 
 .end

src/debug_regs.c

@@ -0,0 +1,179 @@
+#include <stdint.h>
+#include <strings.h>
+
+#include "rtl8710bx.h"
+
+// void dump_hex(const void *data, size_t size, const char *prefix) {
+//   const uint8_t *bytes = (const uint8_t *)data;
+//   for (size_t i = 0; i < size; i++) {
+//     if (i % 16 == 0) printf("\n%s%04zX: ", prefix, i);
+//     printf("%02X ", bytes[i]);
+//   }
+//   printf("\n");
+// }
+
+// void print_clock_config(void) {
+//   printf("\n=== CLOCK CONFIGURATION ===\n");
+
+//   // all releveant regs
+//   printf("\nRegister Values (Raw):\n");
+//   printf("CLK_CTRL1:     0x%08X\n", SYSTEM_CTRL->CLK_CTRL1);
+//   printf("SYSPLL_CTRL0:  0x%08X\n", SYSTEM_CTRL->SYSPLL_CTRL0);
+//   printf("SYSPLL_CTRL1:  0x%08X\n", SYSTEM_CTRL->SYSPLL_CTRL1);
+//   printf("SYSPLL_CTRL2:  0x%08X\n", SYSTEM_CTRL->SYSPLL_CTRL2);
+//   printf("SYSPLL_CTRL3:  0x%08X\n", SYSTEM_CTRL->SYSPLL_CTRL3);
+//   printf("XTAL_CTRL0:    0x%08X\n", SYSTEM_CTRL->XTAL_CTRL0);
+//   printf("XTAL_CTRL1:    0x%08X\n", SYSTEM_CTRL->XTAL_CTRL1);
+//   printf("EFUSE_SYSCFG2: 0x%08X\n", SYSTEM_CTRL->EFUSE_SYSCFG[2]);
+
+//   // CLK_CTRL1
+//   uint32_t clk_ctrl1 = SYSTEM_CTRL->CLK_CTRL1;
+//   printf("\nCLK_CTRL1:\n");
+//   printf("  EXT32K_CK_SEL:    %d\n", (clk_ctrl1 & SYS_CLK_EXT32K_SEL) ? 1 : 0);
+//   printf("  OCP_CPU_CK_SEL:   %d\n", (clk_ctrl1 & SYS_CLK_CPU_CLK_SEL) >> 4);
+//   printf("  EELDR_CK_SEL:     %d\n", (clk_ctrl1 & SYS_CLK_EELDR_SEL) ? 1 : 0);
+
+//   uint32_t syspll_ctrl0 = SYSTEM_CTRL->SYSPLL_CTRL0;
+//   printf("\nSYSPLL_CTRL0:\n");
+//   printf("  CKTST_EN:         %d\n", (syspll_ctrl0 & SYSPLL_CKTST_EN) ? 1 : 0);
+//   printf("  MONCK_SEL:        %d\n",
+//          (syspll_ctrl0 & SYSPLL_MONCK_SEL_MASK) >> 19);
+//   printf("  CP_IOFFSET:       %d\n",
+//          (syspll_ctrl0 & SYSPLL_CP_IOFFSET_MASK) >> 14);
+//   printf("  FREF_EDGE:        %d\n", (syspll_ctrl0 & SYSPLL_FREF_EDGE) ? 1 : 0);
+//   printf("  PLL_EN:           %d\n", (syspll_ctrl0 & SYSPLL_EN) ? 1 : 0);
+//   printf("  LVPC_EN:          %d\n", (syspll_ctrl0 & SYSPLL_LVPC_EN) ? 1 : 0);
+
+//   // SYSPLL_CTRL1
+//   uint32_t syspll_ctrl1 = SYSTEM_CTRL->SYSPLL_CTRL1;
+//   printf("\nSYSPLL_CTRL1:\n");
+//   printf("  CL200M_SEL:       %d\n",
+//          (syspll_ctrl1 & SYSPLL_CL200M_SEL) ? 1 : 0);
+//   printf("  CK500K_SEL:       %d\n",
+//          (syspll_ctrl1 & SYSPLL_CK500K_SEL) ? 1 : 0);
+//   printf("  CK200M_EN:        %d\n", (syspll_ctrl1 & SYSPLL_CK200M_EN) ? 1 : 0);
+//   printf("  CKSDR_EN:         %d\n", (syspll_ctrl1 & SYSPLL_CKSDR_EN) ? 1 : 0);
+//   printf("  CKSDR_DIV:        %d\n",
+//          (syspll_ctrl1 & SYSPLL_CKSDR_DIV_MASK) >> 11);
+//   printf("  CK24P576_EN:      %d\n",
+//          (syspll_ctrl1 & SYSPLL_CK24P576_EN) ? 1 : 0);
+//   printf("  CK22P5792_EN:     %d\n",
+//          (syspll_ctrl1 & SYSPLL_CK22P5792_EN) ? 1 : 0);
+//   printf("  CK83P33M_EN:      %d\n",
+//          (syspll_ctrl1 & SYSPLL_CK83P33M_EN) ? 1 : 0);
+//   printf("  CK_PS_EN:         %d\n", (syspll_ctrl1 & SYSPLL_PS_EN) ? 1 : 0);
+//   printf("  CK_PS_SEL:        %d\n", (syspll_ctrl1 & SYSPLL_PS_SEL_MASK) >> 4);
+
+//   uint32_t syspll_ctrl3 = SYSTEM_CTRL->SYSPLL_CTRL3;
+//   printf("\nSYSPLL_CTRL3:\n");
+//   printf("  DIV_500M:         %d\n", (syspll_ctrl3 & SYSPLL_DIV_MASK) >> 6);
+//   printf("  PHASE_SEL:        %d\n", (syspll_ctrl3 & SYSPLL_PHASE_MASK) >> 3);
+//   printf("  500M_PS_EN:       %d\n",
+//          (syspll_ctrl3 & SYSPLL_500M_PS_EN) ? 1 : 0);
+//   printf("  500M_EN:          %d\n", (syspll_ctrl3 & SYSPLL_500M_EN) ? 1 : 0);
+
+//   // EFUSE_SYSCFG2
+//   uint32_t efuse_syscfg2 = SYSTEM_CTRL->EFUSE_SYSCFG[2];
+//   uint32_t spll_24_15 = (efuse_syscfg2 & SYSCFG2_ANAPAR_SPLL_24_15_MASK) >> 21;
+//   uint32_t spll_05_02 = (efuse_syscfg2 & SYSCFG2_ANAPAR_SPLL_05_02_MASK) >> 16;
+//   uint32_t xtal_stel_sel = (efuse_syscfg2 & SYSCFG2_XTAL_STEL_SEL_MASK) >> 12;
+//   uint32_t xtal_freq_sel = (efuse_syscfg2 & SYSCFG2_XTAL_FREQ_SEL_MASK) >> 8;
+
+//   printf("\nEFUSE_SYSCFG2:\n");
+//   printf("  SPLL 24:15 Config: 0x%03X\n", spll_24_15);
+//   printf("  SPLL 05:02 Config: 0x%X\n", spll_05_02);
+//   printf("  XTAL_STEL_SEL:    0x%X\n", xtal_stel_sel);
+//   printf("  XTAL_FREQ_SEL:    0x%X\n", xtal_freq_sel);
+
+//   printf("\nEFUSE_SYSCFG Array Dump:\n");
+//   for (int i = 0; i < 32; i++) {
+//     uint32_t val = SYSTEM_CTRL->EFUSE_SYSCFG[i];
+//     if (val != 0) {
+//       printf("EFUSE_SYSCFG[%2d]: 0x%08X\n", i, val);
+//     }
+//   }
+
+//   printf("\nSurrounding Registers:\n");
+//   volatile uint32_t *base = (volatile uint32_t *)&SYSTEM_CTRL->EFUSE_SYSCFG[0];
+//   for (int i = -16; i < 48; i++) {
+//     uint32_t val = base[i];
+//     if (val != 0) {
+//       printf("Offset %3d: 0x%08X\n", i * 4, val);
+//     }
+//   }
+
+//   // rom XTAL table
+//   printf("\nXTAL Table Contents (first 16 entries):\n");
+//   const uint32_t *xtal_table = (const uint32_t *)XTAL_TABLE_ROM;
+//   for (int i = 0; i < 16; i++) {
+//     printf("  [%d]: %d (0x%x Hz)\n", i, xtal_table[i], xtal_table[i]);
+//   }
+
+//   // xtal freq
+//   uint32_t xtal_freq = xtal_table[xtal_freq_sel];
+//   printf("\nSelected Crystal:\n");
+//   printf("  Index: %d\n", xtal_freq_sel);
+//   printf("  Frequency: %d Hz (0x%08X)\n", xtal_freq, xtal_freq);
+
+//   uint32_t xtal_ctrl0 = SYSTEM_CTRL->XTAL_CTRL0;
+//   printf("\nXTAL_CTRL0:\n");
+//   printf("  XTAL_EN:          %d\n", (xtal_ctrl0 & XTAL_EN) ? 1 : 0);
+//   printf("  BGMB_EN:          %d\n", (xtal_ctrl0 & XTAL_BGMB_EN) ? 1 : 0);
+//   printf("  GSPL_EN:          %d\n", (xtal_ctrl0 & XTAL_GSPL_EN) ? 1 : 0);
+//   printf("  GMP:              0x%02X\n", (xtal_ctrl0 & XTAL_GMP_MASK) >> 8);
+//   printf("  GMN:              0x%02X\n", (xtal_ctrl0 & XTAL_GMN_MASK) >> 13);
+//   printf("  SC_XI:            0x%02X\n", (xtal_ctrl0 & XTAL_SC_XI_MASK) >> 18);
+//   printf("  SC_XO:            0x%02X\n", (xtal_ctrl0 & XTAL_SC_XO_MASK) >> 24);
+//   printf("  GATED_OK:         %d\n", (xtal_ctrl0 & XTAL_GATED_OK) ? 1 : 0);
+//   printf("  XQSEL_RF:         %d\n", (xtal_ctrl0 & XTAL_XQSEL_RF) ? 1 : 0);
+
+//   uint32_t xtal_ctrl1 = SYSTEM_CTRL->XTAL_CTRL1;
+//   printf("\nXTAL_CTRL1:\n");
+//   printf("  DELAY_SYSPLL:     %d\n", (xtal_ctrl1 & XTAL_DELAY_SYSPLL) ? 1 : 0);
+//   printf("  DELAY_USB:        %d\n", (xtal_ctrl1 & XTAL_DELAY_USB) ? 1 : 0);
+//   printf("  DELAY_WLAFE:      %d\n", (xtal_ctrl1 & XTAL_DELAY_WLAFE) ? 1 : 0);
+//   printf("  AAC_GM_EN:        %d\n", (xtal_ctrl1 & XTAL_AAC_GM_EN) ? 1 : 0);
+//   printf("  AAC_PEAKDET_EN:   %d\n",
+//          (xtal_ctrl1 & XTAL_AAC_PEAKDET_EN) ? 1 : 0);
+//   printf("  DRV_SYSPLL:       %d\n", (xtal_ctrl1 & XTAL_DRV_SYSPLL_MASK) >> 15);
+//   printf("  GATE_SYSPLL:      %d\n", (xtal_ctrl1 & XTAL_GATE_SYSPLL) ? 1 : 0);
+//   printf("  LDO:              %d\n", (xtal_ctrl1 & XTAL_LDO_MASK));
+
+//   // PLL freq
+//   uint32_t pll_base_freq =
+//       (syspll_ctrl1 & SYSPLL_CL200M_SEL) ? 200000000 : 166666666;
+//   printf("\nPLL Frequencies:\n");
+//   printf("  Base:        %d Hz (0x%x)\n", pll_base_freq, pll_base_freq);
+//   printf("  SDR Clock:   %d Hz (if enabled)\n",
+//          pll_base_freq >> (2 - ((syspll_ctrl1 & SYSPLL_CKSDR_DIV_MASK) >> 11)));
+//   printf("  83.33M:      %d Hz (if enabled)\n", 83330000);
+//   printf("  24.576M:     %d Hz (if enabled)\n", 24576000);
+//   printf("  22.5792M:    %d Hz (if enabled)\n", 22579200);
+
+//   // dump clock table
+//   const uint32_t *clk_table = (uint32_t *)CLK_TABLE_ROM;
+//   uint32_t cpu_clock_sel = (clk_ctrl1 & SYS_CLK_CPU_CLK_SEL) >> 4;
+//   uint32_t cpu_freq = clk_table[cpu_clock_sel];
+//   printf("\nCPU Configuration:\n");
+//   printf("  Clock Selection Index: %d\n", cpu_clock_sel);
+//   printf("  Frequency: %d Hz (%d MHz) (0x%x)\n", cpu_freq, cpu_freq / 1000000,
+//          cpu_freq);
+
+//   printf("\nFull table contents:\n");
+//   for (int i = 0; i < 6; i++) {
+//     printf("  [%d]: %d Hz (%d MHz)\n", i, clk_table[i], clk_table[i] / 1000000);
+//   }
+
+//   uint32_t xtal_to_pll = (pll_base_freq / (xtal_freq / 1000));
+//   uint32_t pll_to_cpu =
+//       ((uint32_t)(cpu_freq * 1000000UL) / (pll_base_freq / 1000));
+//   uint32_t xtal_to_cpu =
+//       ((uint32_t)(cpu_freq * 1000000UL) / (xtal_freq / 1000));
+
+//   printf("\nFrequency Relationships (x1000):\n");
+//   printf("  XTAL to PLL Base: %x.%03x\n", xtal_to_pll / 1000,
+//          xtal_to_pll % 1000);
+//   printf("  PLL Base to CPU:  %x.%03x\n", pll_to_cpu / 1000, pll_to_cpu % 1000);
+//   printf("  XTAL to CPU:      %x.%03x\n", xtal_to_cpu / 1000,
+//          xtal_to_cpu % 1000);
+// }

src/main.c

@@ -1,39 +1,28 @@
 #include <stdint.h>
+#include <strings.h>
 
+#include "rom.h"
 #include "rtl8710bx.h"
-
+#include "system_rtl8710bx.h"
-extern uint32_t DiagPrintf(const char *fmt, ...)
+#include "systick.h"
-    __attribute__((format(printf, 1, 2)));
-#define printf DiagPrintf
-
-static inline void delay_cycles(unsigned int count) {
-  __asm volatile(
-      "1: \n"
-      "  subs %[count], %[count], #1 \n"
-      "  bne 1b \n"
-      : [count] "+r"(count)
-      :
-      : "cc");
-}
-static inline void delay_ms(unsigned int ms) {
-  for (unsigned int i = 0; i < ms; i++) {
-    delay_cycles(15625);  // 62500/4 cycles
-  }
-}
 
 int main(void) {
-  printf("hello from main\n");
+  printf("[main]\n");
+  printf("VTOR: 0x%08x\n", SCB->VTOR);
+  printf("SystemCoreClock: %d Hz\n", SystemCoreClock);
+  SysTick_Config(SystemCoreClock / 1000);
 
   PERI_ON->SOC_PERI_FUNC1_EN |= BIT_PERI_GPIO_EN;
   PERI_ON->PESOC_CLK_CTRL |= APBPeriph_GPIO_CLOCK;
-  PINMUX_Config(_PA_0, PINMUX_FN_GPIO);
+  PINMUX_Config(_PA_0, PINMUX_FN_GPIO, GPIO_PuPd_DOWN);
-  PINMUX_ConfigPadPull(_PA_0, GPIO_PuPd_DOWN);
+  // PINMUX_Config(_PA_23, PINMUX_FN_GPIO, GPIO_PuPd_NOPULL);
   GPIOA->DDR |= (1 << 0);
 
+  uint32_t start_t = millis();
   while (1) {
-    GPIOA->DR |= (1 << 0);
+    if ((millis() - start_t) > 1000) {
-    delay_ms(2000);
+      GPIOA->DR ^= (1 << 0);
-    GPIOA->DR &= ~(1 << 0);
+      start_t = millis();
-    delay_ms(2000);
+    }
   }
 }

src/system_rtl8710bx.c

@@ -0,0 +1,43 @@
+#include "system_rtl8710bx.h"
+
+#include <stdint.h>
+
+#include "rtl8710bx.h"
+
+uint32_t SystemCoreClock;
+
+void SystemCoreClockUpdate(void) {
+  uint32_t current_clk_idx =
+      (SYSTEM_CTRL->CLK_CTRL1 & SYS_CLK_CPU_CLK_SEL) >> CPU_CLK_POS;
+  SystemCoreClock = CPU_CLK_TABLE[current_clk_idx];
+}
+
+__attribute__((naked)) void SystemInit(void) {
+  asm volatile(
+      /* zero .bss section */
+      "ldr r0, =_bss_start\n"
+      "ldr r1, =_bss_end\n"
+      "movs r2, #0\n"
+      "1:\n"
+      "cmp r0, r1\n"
+      "itt lt\n"
+      "strlt r2, [r0], #4\n"
+      "blt 1b\n"
+      "\n"
+      /* set up SystemCoreClock */
+      "ldr r0, =%0\n"
+      "ldr r2, =%1\n"
+      "ldr r1, [r0]\n"
+      "ldr r0, =%2\n"
+      "lsrs r1, r1, %3\n"
+      "ldr r2, [r2, r1, lsl #2]\n"
+      "str r2, [r0]\n"
+      "\n"
+      "cpsie i\n"
+      "bl main\n"
+      "b 1b\n" /* if main ever returns */
+      :
+      : "i"(&SYSTEM_CTRL->CLK_CTRL1), "i"(CPU_CLK_TABLE_ADDR),
+        "i"(&SystemCoreClock), "i"(CPU_CLK_POS)
+      : "r0", "r1", "r2", "r3", "memory");
+}

src/systick.c

@@ -0,0 +1,10 @@
+#include "systick.h"
+
+volatile uint32_t systick_millis;
+
+__attribute__((interrupt)) void SysTick_Handler(void) { systick_millis++; }
+
+void Delay_Ms(uint32_t ms) {
+  uint32_t start_ticks = millis();
+  while ((millis() - start_ticks) < ms);
+}