2438 lines
98 KiB
C
2438 lines
98 KiB
C
#ifndef RTL8710BX_H
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#define RTL8710BX_H
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typedef enum IRQn {
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Reset_IRQn = -15, /* Reset Vector, invoked on Power up and warm reset */
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NonMaskableInt_IRQn =
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-14, /* Non maskable Interrupt, cannot be stopped or preempted */
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HardFault_IRQn = -13, /* Hard Fault, all classes of Fault */
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MemoryManagement_IRQn = -12, /* Memory Management, MPU mismatch, including
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Access Violation and No Match */
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BusFault_IRQn = -11, /* Bus Fault, Pre-Fetch-, Memory Access, other
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address/memory Fault */
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UsageFault_IRQn =
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-10, /* Usage Fault, i.e. Undef Instruction, Illegal State Transition */
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SecureFault_IRQn = -9, /* Secure Fault Interrupt */
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SVCall_IRQn = -5, /* System Service Call via SVC instruction */
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DebugMonitor_IRQn = -4, /* Debug Monitor */
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PendSV_IRQn = -2, /* Pendable request for system service */
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SysTick_IRQn = -1, /* System Tick Timer */
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/* RTL8710BX specific interrupts */
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PWR_Wakeup_IRQn = 0, /* System wakeup from power save interrupt */
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WDG_IRQn = 1, /* Window watchdog interrupt */
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TIM0_IRQn = 2, /* Timer 0 global interrupt */
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TIM1_IRQn = 3, /* Timer 1 global interrupt */
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TIM2_IRQn = 4, /* Timer 2 global interrupt */
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TIM3_IRQn = 5, /* Timer 3 global interrupt */
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SPI0_IRQn = 6, /* SPI0 global interrupt */
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GPIO_IRQn = 7, /* GPIO global interrupt */
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UART0_IRQn = 8, /* UART0 global interrupt */
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FLASH_IRQn = 9, /* Flash memory global interrupt */
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UART1_IRQn = 10, /* UART1 global interrupt */
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TIM4_IRQn = 11, /* Timer 4 global interrupt */
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SDIO_IRQn = 12, /* SDIO global interrupt */
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I2S0_PCM0_IRQn = 13, /* I2S0/PCM0 global interrupt */
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TIM5_IRQn = 14, /* Timer 5 global interrupt */
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WLAN_DMA_IRQn = 15, /* WLAN DMA global interrupt */
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WLAN_Protocol_IRQn = 16, /* WLAN protocol global interrupt */
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Crypto_IRQn = 17, /* Cryptography global interrupt */
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SPI1_IRQn = 18, /* SPI1 global interrupt */
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Periph_IRQn = 19, /* Peripheral global interrupt */
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DMA0_Channel0_IRQn = 20, /* DMA0 Channel 0 global interrupt */
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DMA0_Channel1_IRQn = 21, /* DMA0 Channel 1 global interrupt */
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DMA0_Channel2_IRQn = 22, /* DMA0 Channel 2 global interrupt */
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DMA0_Channel3_IRQn = 23, /* DMA0 Channel 3 global interrupt */
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DMA0_Channel4_IRQn = 24, /* DMA0 Channel 4 global interrupt */
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DMA0_Channel5_IRQn = 25, /* DMA0 Channel 5 global interrupt */
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I2C0_IRQn = 26, /* I2C0 global interrupt */
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I2C1_IRQn = 27, /* I2C1 global interrupt */
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UART_Log_IRQn = 28, /* Log UART global interrupt */
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ADC_IRQn = 29, /* ADC global interrupt */
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RDP_IRQn = 30, /* CPU RDP protection interrupt */
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RTC_IRQn = 31, /* RTC global interrupt */
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DMA1_Channel0_IRQn = 32, /* DMA1 Channel 0 global interrupt */
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DMA1_Channel1_IRQn = 33, /* DMA1 Channel 1 global interrupt */
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DMA1_Channel2_IRQn = 34, /* DMA1 Channel 2 global interrupt */
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DMA1_Channel3_IRQn = 35, /* DMA1 Channel 3 global interrupt */
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DMA1_Channel4_IRQn = 36, /* DMA1 Channel 4 global interrupt */
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DMA1_Channel5_IRQn = 37, /* DMA1 Channel 5 global interrupt */
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USB_IRQn = 38, /* USB global interrupt */
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RXI300_IRQn = 39, /* RXI300 global interrupt */
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USB_SIE_IRQn = 40, /* USB SIE global interrupt */
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} IRQn_Type;
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#define __CM4_REV 0x0101 /* Core Revision r0p1 */
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#define __Vendor_SysTickConfig 0U /* Standard ARM SysTick implementation */
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#define __NVIC_PRIO_BITS 4U /* Cortex-M4 uses 4 bits for priority levels */
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#define __VTOR_PRESENT 1U /* Vector Table Offset Register is present */
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#define __MPU_PRESENT 1U /* Memory Protection Unit is present */
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#define __FPU_PRESENT 1U /* Floating Point Unit is present on this M4 */
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#define __FPU_DP 0U /* Single-precision FPU */
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#define __DSP_PRESENT 1U /* DSP extensions are present on M4 */
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#define __SAUREGION_PRESENT 0U /* No Security Attribution Unit */
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#define __PMU_PRESENT 0U /* No Performance Monitoring Unit */
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#define __PMU_NUM_EVENTCNT 0U /* Not applicable since no PMU */
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#define __ICACHE_PRESENT 0U /* No instruction cache */
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#define __DCACHE_PRESENT 0U /* No data cache */
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#define __DTCM_PRESENT 0U /* No DTCM */
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#include "cmsis/core_cm4.h"
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/* Device Specific Peripheral Section */
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/* Analog to Digital Converter */
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typedef struct {
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__IO uint32_t FIFO_READ; /* FIFO read register for channels 0-3 */
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__IO uint32_t CONTROL; /* Main ADC control register */
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__IO uint32_t INTR_EN; /* Interrupt enable register */
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__IO uint32_t INTR_STS; /* Interrupt status register */
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__IO uint32_t COMP_VALUE_L; /* Compare values for channels 0-1 */
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__IO uint32_t COMP_VALUE_H; /* Compare values for channels 2-3 */
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__IO uint32_t COMP_SET; /* Compare configuration register */
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__IO uint32_t POWER; /* Power management register */
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__IO uint32_t ANAPAR_AD0; /* Analog parameters for channel 0 */
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__IO uint32_t ANAPAR_AD1; /* Analog parameters for channel 1 */
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__IO uint32_t ANAPAR_AD2; /* Analog parameters for channel 2 */
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__IO uint32_t ANAPAR_AD3; /* Analog parameters for channel 3 */
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__IO uint32_t ANAPAR_AD4; /* Analog parameters for channel 4 */
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__IO uint32_t ANAPAR_AD5; /* Analog parameters for channel 5 */
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__IO uint32_t CALI_DATA; /* Calibration data register */
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} ADC_TypeDef;
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/* Main backup register structure */
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typedef struct {
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union {
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struct {
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__IO uint32_t SYSTEM_FLAGS : 8; /* System-defined flags */
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__IO uint32_t RTC_BACKUP : 8; /* RTC backup value */
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__IO uint32_t USER_DEFINED : 16; /* User-defined bits */
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} DWORD0;
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__IO uint32_t DWORD[4]; /* 0x138 */
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};
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} BACKUP_REG_TypeDef;
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/* GDMA channel */
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typedef struct {
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__IO uint32_t SAR; /* Source Address, 0x000 */
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__O uint32_t RSAR; /* Source Address Read Back, 0x004 */
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__IO uint32_t DAR; /* Destination Address, 0x008 */
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__O uint32_t RDAR; /* Destination Address Read Back, 0x00C */
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__IO uint32_t LLP; /* Linked List Pointer, 0x010 */
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uint32_t RSVD2;
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__IO uint32_t CTL_LOW; /* Control Low, 0x018 */
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__IO uint32_t CTL_HIGH; /* Control High, 0x01C */
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__IO uint32_t SSTAT; /* Source Status, 0x020 */
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uint32_t RSVD4;
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__IO uint32_t DSTAT; /* Destination Status, 0x028 */
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uint32_t RSVD5;
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__IO uint32_t SSTATAR; /* Source Status Address, 0x030 */
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uint32_t RSVD6;
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__IO uint32_t DSTATAR; /* Destination Status Address, 0x038 */
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uint32_t RSVD7;
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__IO uint32_t CFG_LOW; /* Config Low, 0x040 */
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__IO uint32_t CFG_HIGH; /* Config High, 0x044 */
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__IO uint32_t SGR; /* Source Gather, 0x048 */
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uint32_t RSVD9;
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__IO uint32_t DSR; /* Destination Scatter, 0x050 */
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uint32_t RSVD10; /* 0x054 */
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} GDMA_ChannelTypeDef;
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/* General Direct Memory Access (GDMA) */
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typedef struct {
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GDMA_ChannelTypeDef CH[8]; /* 8 chs, we only have 5 though :) 0x000-0x2BC */
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__I uint32_t RAW_TFR; /* Raw Transfer Status, 0x2C0 */
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uint32_t RSVD0;
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__I uint32_t RAW_BLOCK; /* Raw Block Status, 0x2C8 */
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uint32_t RSVD1;
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__I uint32_t RAW_SRC_TRAN; /* Raw Source Trans Status, 0x2D0 */
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uint32_t RSVD2;
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__I uint32_t RAW_DST_TRAN; /* Raw Dest Trans Status, 0x2D8 */
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uint32_t RSVD3;
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__I uint32_t RAW_ERR; /* Raw Error Status, 0x2E0 */
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uint32_t RSVD4;
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__I uint32_t STATUS_TFR; /* Transfer Status, 0x2E8 */
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uint32_t RSVD5;
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__I uint32_t STATUS_BLOCK; /* Block Status, 0x2F0 */
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uint32_t RSVD6;
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__I uint32_t STATUS_SRC_TRAN; /* Source Trans Status, 0x2F8 */
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uint32_t RSVD7;
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__I uint32_t STATUS_DST_TRAN; /* Dest Trans Status, 0x300 */
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uint32_t RSVD8;
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__I uint32_t STATUS_ERR; /* Error Status, 0x308 */
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uint32_t RSVD9;
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__IO uint32_t MASK_TFR; /* Transfer Mask, 0x310 */
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uint32_t RSVD10;
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__IO uint32_t MASK_BLOCK; /* Block Mask, 0x318 */
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uint32_t RSVD11;
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__IO uint32_t MASK_SRC_TRAN; /* Source Trans Mask, 0x320 */
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uint32_t RSVD12;
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__IO uint32_t MASK_DST_TRAN; /* Dest Trans Mask, 0x328 */
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uint32_t RSVD13;
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__IO uint32_t MASK_ERR; /* Error Mask, 0x330 */
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uint32_t RSVD14;
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__O uint32_t CLEAR_TFR; /* Transfer Clear, 0x338 */
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uint32_t RSVD15;
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__O uint32_t CLEAR_BLOCK; /* Block Clear, 0x340 */
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uint32_t RSVD16;
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__O uint32_t CLEAR_SRC_TRAN; /* Source Trans Clear, 0x348 */
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uint32_t RSVD17;
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__O uint32_t CLEAR_DST_TRAN; /* Dest Trans Clear, 0x350 */
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uint32_t RSVD18;
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__O uint32_t CLEAR_ERR; /* Error Clear, 0x358 */
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uint32_t RSVD19;
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__O uint32_t StatusInt; /* Interrupt Status, 0x360 */
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uint32_t RSVD191;
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__IO uint32_t ReqSrcReg; /* Source SW Request, 0x368 */
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uint32_t RSVD20;
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__IO uint32_t ReqDstReg; /* Dest SW Request, 0x370 */
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uint32_t RSVD21;
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__IO uint32_t SglReqSrcReg; /* Single Source Request, 0x378 */
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uint32_t RSVD22;
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__IO uint32_t SglReqDstReg; /* Single Dest Request, 0x380 */
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uint32_t RSVD23;
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__IO uint32_t LstSrcReg; /* Last Source Request, 0x388 */
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uint32_t RSVD24;
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__IO uint32_t LstDstReg; /* Last Dest Request, 0x390 */
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uint32_t RSVD25;
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__IO uint32_t DmaCfgReg; /* DMA Config, 0x398 */
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uint32_t RSVD26;
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__IO uint32_t ChEnReg; /* Channel Enable, 0x3A0 */
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uint32_t RSVD27;
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__I uint32_t DmaIdReg; /* DMA ID, 0x3A8 */
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uint32_t RSVD28;
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__IO uint32_t DmaTestReg; /* DMA Test, 0x3B0 */
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uint32_t RSVD29;
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} GDMA_TypeDef;
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/* GPIO (General Purpose Input/Output) register definitions */
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typedef struct {
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__IO uint32_t DR; /* Data Register */
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__IO uint32_t DDR; /* Direction Register */
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__IO uint32_t CTRL; /* Control Register */
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} GPIO_Port_TypeDef;
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typedef struct {
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GPIO_Port_TypeDef PORT[4]; /*GPIO IP have 4 ports */
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__IO uint32_t INT_EN; /* GPIO interrupt enable register */
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__IO uint32_t INT_MASK; /* GPIO interrupt mask register */
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__IO uint32_t INT_TYPE; /* interrupt type(level/edge) register */
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__IO uint32_t INT_POLARITY; /* interrupt polarity(Active low/high) register */
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__IO uint32_t INT_STATUS; /* interrupt status register */
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__IO uint32_t INT_RAWSTATUS; /* interrupt status without mask register */
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__IO uint32_t DEBOUNCE; /* interrupt signal debounce register */
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__IO uint32_t PORTA_EOI; /* clear interrupt register */
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__IO uint32_t EXT_PORT[4]; /* GPIO IN read or OUT read back register */
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__IO uint32_t LSSYNC; /* level-sensitive synchronization enable register */
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__IO uint32_t IDCODE; /* GPIO ID code register */
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__IO uint32_t RSVD2; /* Reserved */
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__IO uint32_t VERIDCODE; /* component Version register */
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__IO uint32_t CONFIG2; /* GPIO configuration Register 2 */
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__IO uint32_t CONFIG1; /* GPIO configuration Register 1 */
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} GPIO_TypeDef;
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/* Inter Integrated Circuit Interface */
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typedef struct {
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__IO uint32_t IC_CON; /* Control register */
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__IO uint32_t IC_TAR; /* Target address register */
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__IO uint32_t IC_SAR; /* Slave0 address register */
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__IO uint32_t IC_HS_MADDR; /* HS master mode code address */
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__IO uint32_t IC_DATA_CMD; /* RX/TX data buffer and command */
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__IO uint32_t IC_SS_SCL_HCNT; /* Standard speed SCL high count */
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__IO uint32_t IC_SS_SCL_LCNT; /* Standard speed SCL low count */
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__IO uint32_t IC_FS_SCL_HCNT; /* Fast speed SCL high count */
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__IO uint32_t IC_FS_SCL_LCNT; /* Fast speed SCL low count */
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__IO uint32_t IC_HS_SCL_HCNT; /* High speed SCL high count */
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__IO uint32_t IC_HS_SCL_LCNT; /* High speed SCL low count */
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__I uint32_t IC_INTR_STAT; /* Interrupt status */
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__IO uint32_t IC_INTR_MASK; /* Interrupt mask */
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__I uint32_t IC_RAW_INTR_STAT; /* Raw interrupt status */
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__IO uint32_t IC_RX_TL; /* Receive FIFO threshold */
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__IO uint32_t IC_TX_TL; /* Transmit FIFO threshold */
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__I uint32_t IC_CLR_INTR; /* Clear combined interrupts */
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__I uint32_t IC_CLR_RX_UNDER; /* Clear RX_UNDER interrupt */
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__I uint32_t IC_CLR_RX_OVER; /* Clear RX_OVER interrupt */
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__I uint32_t IC_CLR_TX_OVER; /* Clear TX_OVER interrupt */
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__I uint32_t IC_CLR_RD_REQ; /* Clear RD_REQ interrupt */
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__I uint32_t IC_CLR_TX_ABRT; /* Clear TX_ABRT interrupt */
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__I uint32_t IC_CLR_RX_DONE; /* Clear RX_DONE interrupt */
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__I uint32_t IC_CLR_ACTIVITY; /* Clear ACTIVITY interrupt */
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__I uint32_t IC_CLR_STOP_DET; /* Clear STOP_DET interrupt */
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__I uint32_t IC_CLR_START_DET; /* Clear START_DET interrupt */
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__I uint32_t IC_CLR_GEN_CALL; /* Clear GEN_CALL interrupt */
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__IO uint32_t IC_ENABLE; /* Enable register */
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__I uint32_t IC_STATUS; /* Status register */
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__I uint32_t IC_TXFLR; /* Transmit FIFO level */
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__I uint32_t IC_RXFLR; /* Receive FIFO level */
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__IO uint32_t IC_SDA_HOLD; /* SDA hold time length */
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__I uint32_t IC_TX_ABRT_SOURCE; /* Transmit abort status */
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__IO uint32_t IC_SLV_DATA_NACK_ONLY; /* Generate SLV_DATA_NACK */
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__IO uint32_t IC_DMA_CR; /* DMA control */
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__IO uint32_t IC_DMA_TDLR; /* DMA transmit data level */
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__IO uint32_t IC_DMA_RDLR; /* DMA receive data level */
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__IO uint32_t IC_SDA_SETUP; /* SDA setup */
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__IO uint32_t IC_ACK_GENERAL_CALL; /* ACK general call */
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__IO uint32_t IC_ENABLE_STATUS; /* Enable status */
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/* AmebaZ added New registers */
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__IO uint32_t IC_DMA_CMD; /* DMA command */
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__IO uint32_t IC_DMA_DAT_LEN; /* DMA transmit data length */
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__IO uint32_t IC_DMA_MOD; /* DMA mode */
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__IO uint32_t IC_SLEEP; /* Sleep control */
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__IO uint32_t IC_RSVD1[4]; /* Reserved field */
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__I uint32_t IC_RSVD2[4]; /* Reserved field */
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__I uint32_t IC_RSVD3[4]; /* Reserved field */
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__I uint32_t IC_RSVD4; /* Reserved field */
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__I uint32_t IC_CLR_ADDR_MATCH; /* Clear ADDR_MATCH interrupt */
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__I uint32_t IC_CLR_DMA_I2C_DONE; /* Clear DMA_I2C_DONE interrupt */
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__IO uint32_t IC_FILTER; /* Filter register */
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__I uint32_t IC_RSVD5; /* Reserved field */
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__IO uint32_t IC_SAR1; /* Slave1 address */
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__IO uint32_t IC_DATA_S1; /* Slave1 RX/TX data buffer */
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__I uint32_t IC_COMP_VERSION; /* Component version ID */
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} I2C_TypeDef;
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/* Inter-Integrated Circuit Sound interface */
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typedef struct {
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__IO uint32_t IS_CTL; /* Main I2S control register */
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__IO uint32_t IS_TX_PAGE_PTR; /* TX page pointer */
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__IO uint32_t IS_RX_PAGE_PTR; /* RX page pointer */
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__IO uint32_t IS_SETTING; /* Page size and sample rate settings */
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__IO uint32_t IS_TX_MASK_INT; /* TX interrupt enable */
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__IO uint32_t IS_TX_STATUS_INT; /* TX interrupt status */
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__IO uint32_t IS_RX_MASK_INT; /* RX interrupt enable */
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__IO uint32_t IS_RX_STATUS_INT; /* RX interrupt status */
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__IO uint32_t IS_TX_PAGE_OWN[4]; /* TX page ownership bits */
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__IO uint32_t IS_RX_PAGE_OWN[4]; /* RX page ownership bits */
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} I2S_TypeDef;
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/* Internet Protocol Security (IPsec) */
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typedef struct {
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__IO uint32_t IPSSDAR; /* Source Descriptor Starting Address Register */
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__IO uint32_t IPSDDAR; /* Destination Descriptor Starting Address Register */
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__IO uint32_t IPSCSR; /* Command/Status Register */
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__IO uint32_t IPSCTR; /* Control Register */
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} IPSEC_TypeDef;
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/**
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* NCO32k (Numerically Controlled Oscillator) peripheral structure
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* Controls and monitors the 32KHz clock generation and calibration system
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*/
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typedef struct {
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__IO uint32_t CLK_INFO; // [23:0] Unregulated clock frequency value
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// [24] 32K clock output ready flag
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// [25] 32K calibration ready flag
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__IO uint32_t CLK_OUT; // Expected frequency of NCO calibration output clock
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__IO uint32_t CLK_REF; // Lower 32 bits of reference clock frequency
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// Used for clock output generation and input clock
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// monitoring (ASIC: OSC8M, FPGA: 128K)
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__IO uint32_t CTRL; // [9:0] Reference clock frequency (upper 10 bits)
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// [16] 32K enable
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// [17] Reference clock enable
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// [23:20] 32K monitor
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// [30:24] 32K threshold
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} NCO32k_TypeDef;
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/*
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* 8MHz NCO Register Declaration
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* [0]: function enable
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* [15:1]: expected frequency of nco output clk, unit is 1KHz
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* [31:16] frequency of nco input clk, unit is 1KHz
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*/
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typedef union {
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__IO uint32_t NCOReg; /* 32-bit access */
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} NCO8M_TypeDef;
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/* Peripheral and clock control register definitions */
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typedef struct {
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__IO uint32_t PEON_PWR_CTRL; /* 0x0200 */
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__IO uint32_t PON_ISO_CTRL; /* 0x0204 */
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uint32_t RESERVED0[2]; /* 0x0208-0x020C */
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__IO uint32_t SOC_FUNC_EN; /* 0x0210 */
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__IO uint32_t SOC_HCI_COM_FUNC_EN; /* 0x0214 */
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__IO uint32_t SOC_PERI_FUNC0_EN; /* 0x0218 */
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__IO uint32_t SOC_PERI_FUNC1_EN; /* 0x021C */
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__IO uint32_t SOC_PERI_BD_FUNC0_EN; /* 0x0220 */
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uint32_t RESERVED1[3]; /* 0x0224-0x022C */
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__IO uint32_t PESOC_CLK_CTRL; /* 0x0230 */
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__IO uint32_t PESOC_PERI_CLK_CTRL0; /* 0x0234 */
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__IO uint32_t PESOC_PERI_CLK_CTRL1; /* 0x0238 */
|
|
__IO uint32_t PESOC_CLK_CTRL3; /* 0x023C */
|
|
__IO uint32_t PESOC_HCI_CLK_CTRL0; /* 0x0240 */
|
|
__IO uint32_t PESOC_COM_CLK_CTRL1; /* 0x0244 */
|
|
__IO uint32_t PESOC_HW_ENG_CLK_CTRL; /* 0x0248 */
|
|
uint32_t RESERVED2[1]; /* 0x024C */
|
|
__IO uint32_t PESOC_CLK_SEL; /* 0x0250 */
|
|
uint32_t RESERVED3[6]; /* 0x0254-0x0268 */
|
|
__IO uint32_t UART_NCO_CTRL; /* 0x026C */
|
|
uint32_t RESERVED4[1]; /* 0x0270 */
|
|
__IO uint32_t OSC32K_REG_CTRL0; /* 0x0274 */
|
|
__IO uint32_t OSC32K_REG_CTRL1; /* 0x0278 */
|
|
__IO uint32_t THERMAL_METER_CTRL; /* 0x027C */
|
|
__IO uint32_t GPIO_PINMUX_CTRL[24]; /* 0x0280-0x02DC: Pin Multiplexing */
|
|
__IO uint32_t PON_PINMUX_CTRL; /* 0x02E0 */
|
|
uint32_t RESERVED5[6]; /* 0x02E4-0x02F8 */
|
|
__IO uint32_t FW_PPROTECT_KEY_CTRL; /* 0x02FC */
|
|
uint32_t RESERVED6[1]; /* 0x0300 */
|
|
__IO uint32_t PESOC_SOC_CTRL; /* 0x0304 */
|
|
} PERI_ON_TypeDef;
|
|
|
|
/*
|
|
* AMEBAZ_TIMER Register Declaration
|
|
* TIM1 have 6 CCR registers: bit[15:0] is CCR, bit[31:24] is CCMR
|
|
* TIM3 have 1 CCR registesr: bit[15:0] is CCR, bit[31:24] is CCMR
|
|
* TIM5-8 dont have CCR register
|
|
*/
|
|
|
|
/* RTK Timer (RTIM) registers */
|
|
typedef struct {
|
|
__IO uint32_t EN; /* Timer enable */
|
|
__IO uint32_t CR; /* Main control settings */
|
|
__IO uint32_t DIER; /* DMA/Interrupt configuration */
|
|
__IO uint32_t SR; /* Status flags */
|
|
__IO uint32_t EGR; /* Event generation control */
|
|
__IO uint32_t CNT; /* Counter value */
|
|
__IO uint32_t PSC; /* Clock prescaler */
|
|
__IO uint32_t ARR; /* Auto-reload value */
|
|
__IO uint32_t CCMRx[6]; /* Capture/Compare modes */
|
|
} RTIM_TypeDef;
|
|
|
|
/* RTIM TIM CCR */
|
|
typedef struct {
|
|
__IO uint16_t CCRx; /* TIM capture/compare register */
|
|
__IO uint8_t RSVD; /* TIM capture/compare rsvd register */
|
|
__IO uint8_t CCMRx; /* TIM capture/compare register */
|
|
} RTIM_CCR_TypeDef;
|
|
|
|
/* Real-Time Clock (RTC) registers */
|
|
typedef struct {
|
|
__IO uint32_t TR; /* Time value */
|
|
__IO uint32_t CR; /* Control settings */
|
|
__IO uint32_t ISR; /* Status and initialization */
|
|
__IO uint32_t PRER; /* Clock prescaler */
|
|
__IO uint32_t CALIBR; /* Calibration settings */
|
|
__IO uint32_t ALMR1; /* Alarm 1 configuration */
|
|
__IO uint32_t ALMR2; /* Alarm 2 configuration */
|
|
__IO uint32_t WPR; /* Write protection */
|
|
} RTC_TypeDef;
|
|
|
|
/* Serial Peripheral Interface (SPI) */
|
|
typedef struct {
|
|
__IO uint32_t CTRLR0; /* Control register 0 */
|
|
__IO uint32_t CTRLR1; /* Control register 1 */
|
|
__IO uint32_t SSIENR; /* SSI enable */
|
|
__IO uint32_t MWCR; /* Microwire control */
|
|
__IO uint32_t SER; /* Slave enable */
|
|
__IO uint32_t BAUDR; /* Baud rate select */
|
|
__IO uint32_t TXFTLR; /* TX FIFO threshold level */
|
|
__IO uint32_t RXFTLR; /* RX FIFO threshold level */
|
|
__I uint32_t TXFLR; /* TX FIFO level */
|
|
__I uint32_t RXFLR; /* RX FIFO level */
|
|
__I uint32_t SR; /* Status */
|
|
__IO uint32_t IMR; /* Interrupt mask */
|
|
__I uint32_t ISR; /* Interrupt status */
|
|
__I uint32_t RISR; /* Raw interrupt status */
|
|
__I uint32_t TXOICR; /* TX FIFO overflow interrupt clear */
|
|
__I uint32_t RXOICR; /* RX FIFO overflow interrupt clear */
|
|
__I uint32_t RXUICR; /* RX FIFO underflow interrupt clear */
|
|
__I uint32_t MSTICR; /* Multi-master interrupt clear */
|
|
__I uint32_t ICR; /* Interrupt clear */
|
|
__IO uint32_t DMACR; /* DMA control */
|
|
__IO uint32_t DMATDLR; /* DMA TX data level */
|
|
__IO uint32_t DMARDLR; /* DMA RX data level */
|
|
__I uint32_t IDR; /* Identification */
|
|
__I uint32_t SSI_COMP_VERSION; /* CoreKit version ID */
|
|
__IO uint32_t DR[36]; /* Data register array */
|
|
__IO uint32_t RX_SAMPLE_DLY; /* RX sample delay */
|
|
} SPI_TypeDef;
|
|
|
|
/* SPI Flash Controller (SPIC) */
|
|
typedef struct {
|
|
__IO uint32_t ctrlr0; /* Control register 0 */
|
|
__IO uint32_t ctrlr1; /* Control register 1 */
|
|
__IO uint32_t ssienr; /* SPI enable */
|
|
__IO uint32_t mwcr; /* Reserved */
|
|
__IO uint32_t ser; /* Slave enable */
|
|
__IO uint32_t baudr; /* Baudrate select */
|
|
__IO uint32_t txftlr; /* TX FIFO threshold level */
|
|
__IO uint32_t rxftlr; /* RX FIFO threshold level */
|
|
__IO uint32_t txflr; /* TX FIFO level */
|
|
__IO uint32_t rxflr; /* RX FIFO level */
|
|
__IO uint32_t sr; /* Status register */
|
|
__IO uint32_t imr; /* Interrupt mask */
|
|
__IO uint32_t isr; /* Interrupt status */
|
|
__IO uint32_t risr; /* Raw interrupt status */
|
|
__IO uint32_t txoicr; /* TX FIFO overflow interrupt clear */
|
|
__IO uint32_t rxoicr; /* RX FIFO overflow interrupt clear */
|
|
__IO uint32_t rxuicr; /* RX FIFO underflow interrupt clear */
|
|
__IO uint32_t msticr; /* Master error interrupt clear */
|
|
__IO uint32_t icr; /* Interrupt clear */
|
|
__IO uint32_t dmacr; /* Reserved */
|
|
__IO uint32_t dmatdlr; /* Reserved */
|
|
__IO uint32_t dmardlr; /* Reserved */
|
|
__IO uint32_t idr; /* Identification register */
|
|
__IO uint32_t spi_flash_version; /* Version ID */
|
|
union {
|
|
__IO uint8_t byte;
|
|
__IO uint16_t half;
|
|
__IO uint32_t word;
|
|
} dr[32]; /* Data register array */
|
|
__IO uint32_t rd_fast_single; /* Flash fast read command */
|
|
__IO uint32_t rd_dual_o; /* Flash dual output read */
|
|
__IO uint32_t rd_dual_io; /* Flash dual I/O read */
|
|
__IO uint32_t rd_quad_o; /* Flash quad output read */
|
|
__IO uint32_t rd_quad_io; /* Flash quad I/O read */
|
|
__IO uint32_t wr_single; /* Flash page program */
|
|
__IO uint32_t wr_dual_i; /* Flash dual input program */
|
|
__IO uint32_t wr_dual_ii; /* Flash dual addr/data program */
|
|
__IO uint32_t wr_quad_i; /* Flash quad input program */
|
|
__IO uint32_t wr_quad_ii; /* Flash quad addr/data program */
|
|
__IO uint32_t wr_enable; /* Flash write enable */
|
|
__IO uint32_t rd_status; /* Flash read status */
|
|
__IO uint32_t ctrlr2; /* Control register 2 */
|
|
__IO uint32_t fbaudr; /* Fast baudrate select */
|
|
__IO uint32_t addr_length; /* Address length */
|
|
__IO uint32_t auto_length; /* Auto address length */
|
|
__IO uint32_t valid_cmd; /* Valid command */
|
|
__IO uint32_t flash_size; /* Flash size */
|
|
__IO uint32_t flush_fifo; /* Flush FIFO */
|
|
} SPIC_TypeDef;
|
|
|
|
/* AMEBAZ_CACHE Register Declaration */
|
|
typedef struct {
|
|
__IO uint32_t SPICC_EN; /* Enable control */
|
|
__IO uint32_t SPICC_FLUSH; /* Cache flush control */
|
|
__IO uint32_t SPICC_INTR; /* Interrupt status/control */
|
|
__IO uint32_t SPICC_RST_CUNT; /* Reset counter */
|
|
__IO uint32_t SPICC_RD_EVT_CUNT; /* Read events counter */
|
|
__IO uint32_t SPICC_HIT_EVT_CUNT; /* Cache hit counter */
|
|
__IO uint32_t SPICC_HIT_LSTW_EVT_CUNT; /* Last-way hit counter */
|
|
__IO uint32_t SPICC_RD_PEND_CUNT; /* Pending read counter */
|
|
} SPIC_CACHE_TypeDef;
|
|
|
|
/* Control register definitions for system-level configurations */
|
|
typedef struct {
|
|
/* 0x0000 - Power/Isolation Control */
|
|
union {
|
|
struct {
|
|
__IO uint16_t PWR_CTRL; /* 0x0000 */
|
|
__IO uint16_t ISO_CTRL; /* 0x0002 */
|
|
} PWR_ISO;
|
|
__IO uint32_t PWR_ISO_CTRL; /* 0x0000 */
|
|
};
|
|
|
|
uint32_t RESERVED0[1]; /* 0x0004 */
|
|
__IO uint32_t FUNC_EN; /* 0x0008 */
|
|
uint32_t RESERVED1[1]; /* 0x000C */
|
|
__IO uint32_t CLK_CTRL0; /* 0x0010 */
|
|
__IO uint32_t CLK_CTRL1; /* 0x0014 */
|
|
|
|
uint32_t RESERVED2[2]; /* 0x0018-0x001C */
|
|
|
|
/* EFUSE System Configuration Registers */
|
|
__IO uint32_t EFUSE_SYSCFG[8]; /* 0x0020-0x003C */
|
|
|
|
__IO uint32_t REGU_CTRL0; /* 0x0040 */
|
|
uint32_t RESERVED3[1]; /* 0x0044 */
|
|
__IO uint32_t SWR_CTRL0; /* 0x0048 */
|
|
__IO uint32_t SWR_CTRL1; /* 0x004C */
|
|
|
|
uint32_t RESERVED4[4]; /* 0x0050-0x005C */
|
|
|
|
/* Crystal Control Registers */
|
|
__IO uint32_t XTAL_CTRL0; /* 0x0060 */
|
|
__IO uint32_t XTAL_CTRL1; /* 0x0064 */
|
|
__IO uint32_t XTAL_CTRL2; /* 0x0068 */
|
|
|
|
uint32_t RESERVED5[1]; /* 0x006C */
|
|
|
|
/* System PLL Control Registers */
|
|
__IO uint32_t SYSPLL_CTRL0; /* 0x0070: Main System PLL */
|
|
__IO uint32_t SYSPLL_CTRL1; /* 0x0074: Clock Distribution Control */
|
|
__IO uint32_t SYSPLL_CTRL2; /* 0x0078: ADC PLL Control */
|
|
__IO uint32_t SYSPLL_CTRL3; /* 0x007C: Flash SPI PLL Control */
|
|
|
|
uint32_t RESERVED6[4]; /* 0x0080-0x008C */
|
|
|
|
__IO uint32_t ANA_TIM_CTRL; /* 0x0090 */
|
|
__IO uint32_t DSLP_TIM_CTRL; /* 0x0094 */
|
|
__IO uint32_t DSLP_TIM_CAL_CTRL; /* 0x0098 */
|
|
|
|
uint32_t RESERVED7[2]; /* 0x009C-0x00A0 */
|
|
|
|
__IO uint32_t DEBUG_CTRL; /* 0x00A0 */
|
|
__IO uint32_t PINMUX_CTRL; /* 0x00A4 */
|
|
__IO uint32_t GPIO_DSTBY_WAKE_CTRL0; /* 0x00A8 */
|
|
__IO uint32_t GPIO_DSTBY_WAKE_CTRL1; /* 0x00AC */
|
|
|
|
uint32_t RESERVED8[3]; /* 0x00B0-0x00B8 */
|
|
|
|
__IO uint32_t DEBUG_REG; /* 0x00BC */
|
|
|
|
uint32_t RESERVED9[8]; /* 0x00C0-0x00DC */
|
|
|
|
__IO uint32_t EEPROM_CTRL0; /* 0x00E0 */
|
|
__IO uint32_t EEPROM_CTRL1; /* 0x00E4 */
|
|
__IO uint32_t EFUSE_CTRL; /* 0x00E8 */
|
|
__IO uint32_t EFUSE_TEST; /* 0x00EC */
|
|
__IO uint32_t OSC32K_CTRL; /* 0x00F0 */
|
|
__IO uint32_t OSC32K_RCAL; /* 0x00F4 */
|
|
__IO uint32_t DSTBY_INFO0; /* 0x00F8 */
|
|
__IO uint32_t DSTBY_INFO1; /* 0x00FC */
|
|
__IO uint32_t SLP_WAKE_EVENT_MSK0; /* 0x0100 */
|
|
__IO uint32_t SLP_WAKE_EVENT_MSK1; /* 0x0104 */
|
|
__IO uint32_t SLP_WAKE_EVENT_STATUS0; /* 0x0108 */
|
|
__IO uint32_t SLP_WAKE_EVENT_STATUS1; /* 0x010C */
|
|
__IO uint32_t SNF_WAKE_EVENT_MSK0; /* 0x0110 */
|
|
__IO uint32_t SNF_WAKE_EVENT_STATUS; /* 0x0114 */
|
|
__IO uint32_t PWRMGT_CTRL; /* 0x0118 */
|
|
|
|
uint32_t RESERVED10[1]; /* 0x011C */
|
|
|
|
__IO uint32_t PWRMGT_OPTION; /* 0x0120 */
|
|
__IO uint32_t PWRMGT_OPTION_EXT; /* 0x0124 */
|
|
|
|
uint32_t RESERVED11[2]; /* 0x0128-0x012C */
|
|
|
|
__IO uint32_t DSLP_WEVENT; /* 0x0130 */
|
|
__IO uint32_t PERI_MONITOR; /* 0x0134 */
|
|
__IO uint32_t NORESET_FF; /* 0x0138 */
|
|
|
|
uint32_t RESERVED12[45]; /* 0x013C-0x01EC */
|
|
|
|
__IO uint32_t SYSTEM_CFG0; /* 0x01F0 */
|
|
__IO uint32_t SYSTEM_CFG1; /* 0x01F4 */
|
|
__IO uint32_t SYSTEM_CFG2; /* 0x01F8 */
|
|
} SYSTEM_CTRL_TypeDef;
|
|
|
|
/* Universal asynchronous receiver-transmitter (UART) */
|
|
typedef struct {
|
|
__IO uint32_t DLL; /* Divisor Latch (unused in Amebaz) */
|
|
__IO uint32_t DLH_INTCR; /* Interrupt Enable */
|
|
__IO uint32_t INTID; /* Interrupt Identification */
|
|
__IO uint32_t LCR; /* Line Control */
|
|
__IO uint32_t MCR; /* Modem Control */
|
|
__I uint32_t LSR; /* Line Status */
|
|
__I uint32_t MDSR; /* Modem Status */
|
|
__IO uint32_t SPR; /* Scratch Pad */
|
|
__IO uint32_t STSR; /* STS Register */
|
|
__IO uint32_t RB_THR; /* Receive Buffer/Transmit Holding */
|
|
__IO uint32_t MISCR; /* Misc Control */
|
|
__IO uint32_t TXPLSR; /* IrDA TX Pulse Width Control */
|
|
|
|
__IO uint32_t RXPLSR; /* IrDA RX Pulse Width Control */
|
|
__IO uint32_t BAUDMONR; /* Baud Monitor */
|
|
__IO uint32_t RSVD2; /* Reserved */
|
|
__IO uint32_t DBG_UART; /* Debug */
|
|
|
|
/* Power save features */
|
|
__IO uint32_t RX_PATH; /* RX Path Control */
|
|
__IO uint32_t MON_BAUD_CTRL; /* Monitor Baud Rate Control */
|
|
__IO uint32_t MON_BAUD_STS; /* Monitor Baud Rate Status */
|
|
__IO uint32_t MON_CYC_NUM; /* Monitor Cycle Number */
|
|
__IO uint32_t RX_BYTE_CNT; /* RX Byte Counter */
|
|
|
|
__IO uint32_t FCR; /* FIFO Control */
|
|
} UART_TypeDef;
|
|
|
|
/* USB System-on-Chip (USOC) */
|
|
typedef struct {
|
|
__IO uint32_t SIE_CR; /* SIE control */
|
|
__IO uint32_t CLK_RST_CTRL; /* Clock and reset control */
|
|
__IO uint32_t CHANN_CTRL; /* Channel control */
|
|
__IO uint32_t BUFF_SIZE_CTRL; /* TX/RX buffer size control */
|
|
__IO uint32_t TXBD_BAR; /* TX buffer descriptor base address */
|
|
__IO uint32_t RXBD_BAR; /* RX buffer descriptor base address */
|
|
__IO uint32_t RING_SIZE_CTRL; /* Ring size control */
|
|
__IO uint32_t RSVD1; /* Reserved */
|
|
__I uint32_t TXBD_HW_IDX; /* TX hardware index */
|
|
__IO uint32_t TXBD_SW_IDX; /* TX software index */
|
|
__I uint32_t RXBD_HW_IDX; /* RX hardware index */
|
|
__IO uint32_t RXBD_SW_IDX; /* RX software index */
|
|
__IO uint32_t INTR_MASK; /* Interrupt mask */
|
|
__IO uint32_t INTR_CLR; /* Interrupt clear */
|
|
__IO uint32_t INTR_STAT; /* Interrupt status */
|
|
__IO uint32_t RSVD2; /* Reserved */
|
|
__IO uint32_t TX_MIT; /* TX mitigation */
|
|
__IO uint32_t RX_MIT; /* RX mitigation */
|
|
__IO uint32_t RSVD3[2]; /* Reserved */
|
|
__IO uint32_t IOREG_MAR; /* Host device access */
|
|
__IO uint32_t RSVD4[3]; /* Reserved */
|
|
__IO uint32_t TX_MAIN_BUF_CTRL; /* TX main buffer control */
|
|
__IO uint32_t TX_DEST_BUF_CTRL; /* TX destination buffer control */
|
|
__IO uint32_t RX_MAIN_BUF_CTRL; /* RX main buffer control */
|
|
__IO uint32_t RX_SRC_BUF_CTRL; /* RX source buffer control */
|
|
__IO uint32_t TX_STUCK_TIMER; /* TX stuck timer */
|
|
__IO uint32_t RX_STUCK_TIMER; /* RX stuck timer */
|
|
__IO uint32_t QOS_CTRL; /* QoS control */
|
|
} USOC_TypeDef;
|
|
|
|
/* 0x0000h ~ 0x00FFh System Configuration */
|
|
/* System Configuration: 0x0000h ~ 0x00FFh */
|
|
typedef struct {
|
|
__IO uint16_t SYS_ISO_CTRL; /* 0x0000, System power isolation ctrl */
|
|
__IO uint16_t WL_CLK_CTRL; /* 0x0002, WiFi clock gating and power ctrl */
|
|
__IO uint16_t SYS_FUNC_EN; /* 0x0004, System function blocks 1/0 */
|
|
__IO uint16_t RESERVED1; /* 0x0006 */
|
|
__IO uint16_t SYS_CLKR; /* 0x0008, System clock source sel */
|
|
__IO uint16_t RESERVED2[36]; /* 0x000A-0x004F */
|
|
__IO uint32_t AFE_CTRL; /* 0x0050, Analog front-end control settings? */
|
|
__IO uint32_t RESERVED3[2]; /* 0x0054-0x0058 */
|
|
__IO uint32_t WL_RF_PSS; /* 0x005C, RF power saving ctrl */
|
|
__IO uint32_t RESERVED4[3]; /* 0x0060-0x0068 */
|
|
__IO uint32_t EFUSE_INDIRECT_CTRL; /* 0x006C, eFuse indirect access control */
|
|
__IO uint32_t WL_PIN_FUNC_CTRL; /* 0x0070, WiFi GPIO func ctrl? */
|
|
__IO uint32_t RESERVED5[3]; /* 0x0074-0x007C */
|
|
__IO uint32_t HIMR0; /* 0x0080, Host interrupt mask register 0 */
|
|
__IO uint32_t HISR0; /* 0x0084, Host interrupt status flags 0 */
|
|
__IO uint32_t HCI_OPT_CTRL; /* 0x0088, Host controller interface opts */
|
|
__IO uint32_t RESERVED6; /* 0x008C */
|
|
__IO uint32_t FW_CTRL_V1; /* 0x0090, Firmware control and status */
|
|
__IO uint32_t RESERVED7[2]; /* 0x0094-0x0098 */
|
|
__IO uint32_t
|
|
USB_HOST_INDIRECT_DATA; /* 0x009C, USB host indirect access data */
|
|
__IO uint32_t RESERVED8[20]; /* 0x00A0-0x00EC */
|
|
__IO uint32_t EEPROM_CTRL; /* 0x00E0, EEPROM access control */
|
|
__IO uint32_t RESERVED9[3]; /* 0x00E4-0x00EC */
|
|
__IO uint32_t WL_STATUS; /* 0x00F0, WiFi subsystem status */
|
|
__IO uint32_t FW_DBG_STATUS; /* 0x00F4, Firmware debug info */
|
|
__IO uint32_t
|
|
USB_HOST_INDIRECT_ADDR; /* 0x00F8, USB host indirect access address */
|
|
__IO uint32_t SYS_CFG2; /* 0x00FC, REG_SYS_CFG2_8710B */
|
|
} WIFI_SYS_TypeDef;
|
|
|
|
/* 0x0100h ~ 0x01FFh MACTOP General Configuration */
|
|
typedef struct {
|
|
__IO uint32_t CR; /* 0x0100 Control Register */
|
|
__IO uint32_t PBP; /* 0x0104 Packet Buffer Parameter */
|
|
__IO uint16_t PKT_BUFF_ACCESS_CTRL; /* 0x0106 Packet Buffer Access Control */
|
|
uint16_t RESERVED0; /* 0x0108-0x0109 */
|
|
__IO uint32_t TRXDMA_CTRL; /* 0x010C TRX DMA Control */
|
|
uint8_t RESERVED1[4]; /* 0x0110-0x0113 */
|
|
__IO uint32_t TRXFF_BNDY; /* 0x0114 TRX FIFO Boundary */
|
|
__I uint32_t TRXFF_STATUS; /* 0x0118 TRX FIFO Status */
|
|
__I uint32_t RXFF_PTR; /* 0x011C RX FIFO Pointer */
|
|
uint8_t RESERVED2[12]; /* 0x0120-0x012B */
|
|
__IO uint8_t CPWM; /* 0x012C Control Power Management */
|
|
uint8_t RESERVED3[3]; /* 0x012D-0x012F */
|
|
__IO uint32_t FWIMR; /* 0x0130 FW Interrupt Mask Register */
|
|
__IO uint32_t FWISR; /* 0x0134 FW Interrupt Status Register */
|
|
__IO uint32_t FTIMR; /* 0x0138 FW Timer Interrupt Mask Register */
|
|
__IO uint32_t FTISR; /* 0x013C FW Timer Interrupt Status Register */
|
|
__IO uint16_t PKTBUF_DBG_CTRL; /* 0x0140 Packet Buffer Debug Control */
|
|
__IO uint16_t RXPKTBUF_CTRL; /* 0x0142 RX Packet Buffer Control */
|
|
__I uint32_t PKTBUF_DBG_DATA_L; /* 0x0144 Packet Buffer Debug Data Low */
|
|
__I uint32_t PKTBUF_DBG_DATA_H; /* 0x0148 Packet Buffer Debug Data High */
|
|
__IO uint32_t TC0_CTRL; /* 0x0150 TC0 Control Register */
|
|
__IO uint32_t TC1_CTRL; /* 0x0154 TC1 Control Register */
|
|
__IO uint32_t TC2_CTRL; /* 0x0158 TC2 Control Register */
|
|
__IO uint32_t TC3_CTRL; /* 0x015C TC3 Control Register */
|
|
__IO uint32_t TC4_CTRL; /* 0x0160 TC4 Control Register */
|
|
__IO uint32_t TCUNIT_BASE; /* 0x0164 TC Unit Base */
|
|
__IO uint32_t RSVD3; /* 0x0168 Reserved */
|
|
uint8_t RESERVED5[0x34]; /* 0x016C-0x019F */
|
|
__I uint8_t C2HEVT_MSG_NORMAL; /* 0x01A0 C2H Event Message Normal */
|
|
__I uint8_t C2HEVT_CMD_SEQ; /* 0x01A1 C2H Event Command Sequence */
|
|
__I uint8_t
|
|
C2HEVT_CMD_CONTENT[12]; /* 0x01A2-0x01AD C2H Event Command Content */
|
|
__I uint8_t C2HEVT_CMD_LEN; /* 0x01AE C2H Event Command Length */
|
|
__O uint8_t C2HEVT_CLEAR; /* 0x01AF C2H Event Clear */
|
|
__IO uint32_t MCUTST_1; /* 0x01C0 MCU Test 1 */
|
|
uint8_t RESERVED6[3]; /* 0x01C4-0x01C6 */
|
|
__IO uint8_t MCUTST_WOWLAN; /* 0x01C7 MCU Test WOWLAN */
|
|
__IO uint32_t FMETHR; /* 0x01C8 FW Message Exchange Threshold */
|
|
__IO uint32_t HMETFR; /* 0x01CC Host Message Exchange Threshold */
|
|
__IO uint32_t HMEBOX_0; /* 0x01D0 Host Message Box 0 */
|
|
__IO uint32_t HMEBOX_1; /* 0x01D4 Host Message Box 1 */
|
|
__IO uint32_t HMEBOX_2; /* 0x01D8 Host Message Box 2 */
|
|
__IO uint32_t HMEBOX_3; /* 0x01DC Host Message Box 3 */
|
|
__IO uint32_t LLT_INIT; /* 0x01E0 LLT Init */
|
|
uint8_t RESERVED7[0xC]; /* 0x01E4-0x01EF */
|
|
__IO uint32_t HMEBOX_EXT0; /* 0x01F0 Host Message Box Extension 0 */
|
|
__IO uint32_t HMEBOX_EXT1; /* 0x01F4 Host Message Box Extension 1 */
|
|
__IO uint32_t HMEBOX_EXT2; /* 0x01F8 Host Message Box Extension 2 */
|
|
__IO uint32_t HMEBOX_EXT3; /* 0x01FC Host Message Box Extension 3 */
|
|
} WIFI_MAC_TypeDef;
|
|
|
|
/* 0x0200h ~ 0x027Fh TXDMA Configuration */
|
|
typedef struct {
|
|
__IO uint32_t RQPN; /* 0x0200 Release Queue Page Number */
|
|
__IO uint32_t FIFOPAGE; /* 0x0204 FIFO Page */
|
|
__IO uint32_t TDECTRL; /* 0x0208 TX DMA Engine Control */
|
|
__IO uint32_t TXDMA_OFFSET_CHK; /* 0x020C TX DMA Offset Check */
|
|
__I uint32_t TXDMA_STATUS; /* 0x0210 TX DMA Status */
|
|
__IO uint32_t RQPN_NPQ; /* 0x0214 Release Queue Page Number NPQ */
|
|
uint8_t RESERVED1[12]; /* 0x0218-0x0223 */
|
|
__IO uint32_t AUTO_LLT; /* 0x0224 Auto LLT */
|
|
__IO uint32_t DWBCN1_CTRL; /* 0x0228 Beacon 1 TXDMA control? */
|
|
uint8_t RESERVED3[84]; /* 0x022C-0x027F */
|
|
} WIFI_TXDMA_TypeDef;
|
|
/* 0x0280h ~ 0x02FFh RXDMA Configuration */
|
|
typedef struct {
|
|
__IO uint32_t AGG_PG_TH; /* 0x0280 RX DMA Aggregation Page Threshold */
|
|
__IO uint32_t RXPKT_NUM; /* 0x0284 The number of packets in RXPKTBUF */
|
|
__IO uint16_t RXDMA_CONTROL; /* 0x0286 Control the RX DMA */
|
|
uint8_t RESERVED1[1]; /* 0x0287 */
|
|
__IO uint32_t RXDMA_STATUS; /* 0x0288 RX DMA Status */
|
|
uint8_t RESERVED2[4]; /* 0x028C-0x028F */
|
|
__IO uint32_t RXDMA_MODE; /* 0x0290 RXDMA Mode */
|
|
uint8_t RESERVED3[0x28]; /* 0x0294-0x02BB */
|
|
__IO uint32_t EARLY_MODE_CONTROL; /* 0x02BC Early Mode Control */
|
|
uint8_t RESERVED4[0x30]; /* 0x02C0-0x02EF */
|
|
__IO uint32_t RSVD5; /* 0x02F0 Reserved */
|
|
uint8_t RESERVED5[0xC]; /* 0x02F4-0x02FF */
|
|
} WIFI_RXDMA_TypeDef;
|
|
|
|
/* 0x0300h ~ 0x03FFh LxBUS hal_com_reg.h */
|
|
/**
|
|
* TODO: this is VERY LIKELY wrong, lxbus_ops.o
|
|
* DMA descriptors aren't arranged sequentially
|
|
* spacing between TX descriptors is unusual
|
|
* 32K control register (at 0x3D9)???
|
|
*/
|
|
// void __fastcall ROM_WIFI_InitLxDma_patch(rtw_tx_ring *tx_ring, rtw_rx_ring
|
|
// *rx_ring, uint32_t test_mode)
|
|
// {
|
|
// dword_40080300 &= ~0x100u;
|
|
// dword_400803E8 = 0xFFFFFF;
|
|
// word_40080380 = 0x1004;
|
|
// word_40080382 = 0x2004;
|
|
// word_40080384 = 0x1004;
|
|
// word_40080386 = 0x1004;
|
|
// word_40080388 = 0x1004;
|
|
// word_4008038A = 0x1004;
|
|
// word_4008038C = 0x1002;
|
|
// word_4008038E = 0x1002;
|
|
// word_40080390 = 0x1002;
|
|
// word_40080392 = 0x1002;
|
|
// word_40080394 = 0x1002;
|
|
// word_40080396 = 0x1002;
|
|
// word_40080398 = 0x1002;
|
|
// word_4008039A = 0x1002;
|
|
// dword_40080318 = (int)tx_ring->desc;
|
|
// dword_40080320 = (int)tx_ring[1].desc;
|
|
// dword_40080328 = (int)tx_ring[2].desc;
|
|
// dword_40080330 = (int)tx_ring[3].desc;
|
|
// dword_40080308 = (int)tx_ring[4].desc;
|
|
// dword_40080310 = (int)tx_ring[5].desc;
|
|
// dword_40080340 = (int)tx_ring[6].desc;
|
|
// dword_40080338 = (int)rx_ring->desc;
|
|
// dword_4008020C |= 0x10000000u;
|
|
// }
|
|
/* 0x0300h ~ 0x03FFh LxBUS Registers */
|
|
typedef struct {
|
|
/* 0x0300 - Control Register */
|
|
__IO uint32_t CTRL; /* 0x0300 - Control register */
|
|
__IO uint32_t RESERVED1[1]; /* 0x0304 */
|
|
__IO uint32_t TX4_DESC; /* 0x0308 - TX Ring 4 Descriptor */
|
|
__IO uint32_t RESERVED2[1]; /* 0x030C */
|
|
__IO uint32_t TX5_DESC; /* 0x0310 - TX Ring 5 Descriptor */
|
|
__IO uint32_t RESERVED3[1]; /* 0x0314 */
|
|
__IO uint32_t TX0_DESC; /* 0x0318 - TX Ring 0 Descriptor */
|
|
__IO uint32_t RESERVED4[1]; /* 0x031C */
|
|
__IO uint32_t TX1_DESC; /* 0x0320 - TX Ring 1 Descriptor */
|
|
__IO uint32_t RESERVED5[1]; /* 0x0324 */
|
|
__IO uint32_t TX2_DESC; /* 0x0328 - TX Ring 2 Descriptor */
|
|
__IO uint32_t RESERVED6[1]; /* 0x032C */
|
|
__IO uint32_t TX3_DESC; /* 0x0330 - TX Ring 3 Descriptor */
|
|
__IO uint32_t RESERVED7[1]; /* 0x0334 */
|
|
__IO uint32_t RX_DESC; /* 0x0338 - RX Ring Descriptor */
|
|
__IO uint32_t RESERVED8[1]; /* 0x033C */
|
|
__IO uint32_t TX6_DESC; /* 0x0340 - TX Ring 6 Descriptor */
|
|
__IO uint32_t RESERVED9[15]; /* 0x0344-0x037F */
|
|
|
|
/* DMA Configuration Registers */
|
|
__IO uint16_t DMA_CFG[14]; /* 0x0380-0x039B - DMA Configuration registers */
|
|
__IO uint8_t RESERVED10[61]; /* 0x039C-0x03D8 */
|
|
|
|
/* 32K Control Register */
|
|
__IO uint8_t K32_CTRL; /* 0x03D9 - 32K Control register */
|
|
__IO uint8_t RESERVED11[14]; /* 0x03DA-0x03E7 */
|
|
|
|
/* Additional Control Registers */
|
|
__IO uint32_t INT_MASK; /* 0x03E8 - Interrupt Mask */
|
|
__I uint32_t INT_STATUS; /* 0x03EC - Interrupt Status */
|
|
} WIFI_LXBUS_TypeDef;
|
|
|
|
/* 0x0400h ~ 0x047Fh Protocol Configuration */
|
|
typedef struct {
|
|
/* Queue Information Registers */
|
|
__IO uint32_t VOQ_INFORMATION; /* 0x0400 VO Queue Information */
|
|
__IO uint32_t VIQ_INFORMATION; /* 0x0404 VI Queue Information */
|
|
__IO uint32_t BEQ_INFORMATION; /* 0x0408 BE Queue Information */
|
|
__IO uint32_t BKQ_INFORMATION; /* 0x040C BK Queue Information */
|
|
__IO uint32_t MGQ_INFORMATION; /* 0x0410 MG Queue Information */
|
|
__IO uint32_t HGQ_INFORMATION; /* 0x0414 HG Queue Information */
|
|
__IO uint32_t BCNQ_INFORMATION; /* 0x0418 BCN Queue Information */
|
|
__I uint16_t TXPKT_EMPTY; /* 0x041A TX Packet Empty */
|
|
uint8_t RESERVED1[4]; /* 0x041C-0x041F */
|
|
|
|
/* Control Registers */
|
|
__IO uint32_t FWHW_TXQ_CTRL; /* 0x0420 FWHW TX Queue Control */
|
|
__IO uint8_t HWSEQ_CTRL; /* 0x0423 HW Sequence Control */
|
|
__IO uint8_t TXPKTBUF_BCNQ_BDNY; /* 0x0424 TX Packet Buffer BCNQ Boundary */
|
|
__IO uint8_t TXPKTBUF_MGQ_BDNY; /* 0x0425 TX Packet Buffer MGQ Boundary */
|
|
__IO uint8_t LIFECTRL_CTRL; /* 0x0426 Life Control */
|
|
__IO uint8_t MULTI_BCNQ_OFFSET; /* 0x0427 Multi BCNQ Offset */
|
|
__IO uint16_t SPEC_SIFS; /* 0x0428 Specific SIFS */
|
|
__IO uint16_t RL; /* 0x042A Retry Limit */
|
|
__IO uint32_t TXBF_CTRL; /* 0x042C TX Beamforming Control */
|
|
|
|
/* Frame Rate Control */
|
|
__IO uint64_t
|
|
DARFRC; /* 0x0430-0x0437 Data Auto Response Frame Rate Control */
|
|
__IO uint64_t
|
|
RARFRC; /* 0x0438-0x043F Response Auto Response Frame Rate Control */
|
|
__IO uint32_t RRSR; /* 0x0440 Response Rate Set */
|
|
__IO uint64_t ARFR0; /* 0x0444-0x044B Auto Response Frame Rate 0 */
|
|
__IO uint64_t ARFR1; /* 0x044C-0x0453 Auto Response Frame Rate 1 */
|
|
__IO uint16_t CCK_CHECK; /* 0x0454 CCK Check */
|
|
__IO uint16_t AMPDU_MAX_TIME; /* 0x0456 AMPDU Max Time */
|
|
__IO uint8_t
|
|
TXPKTBUF_BCNQ_BDNY1; /* 0x0457 TX Packet Buffer BCNQ Boundary 1 */
|
|
/* AMPDU and Buffer Control */
|
|
__IO uint32_t AMPDU_MAX_LENGTH; /* 0x0458 AMPDU Max Length */
|
|
uint8_t RESERVED2[1]; /* 0x045C */
|
|
__IO uint8_t
|
|
TXPKTBUF_WMAC_LBK_BF_HD; /* 0x045D TX Packet Buffer WMAC LBK BF HD */
|
|
uint8_t RESERVED3[1]; /* 0x045E */
|
|
__IO uint8_t NDPA_OPT_CTRL; /* 0x045F NDPA Option Control */
|
|
__IO uint32_t FAST_EDCA_CTRL; /* 0x0460 Fast EDCA Control */
|
|
__IO uint8_t RD_RESP_PKT_TH; /* 0x0463 RD Response Packet Threshold */
|
|
uint8_t RESERVED4[0x1A]; /* 0x0464-0x047D */
|
|
__IO uint8_t SPC_W_PTR; /* 0x047E SPC Write Pointer */
|
|
__IO uint8_t SPC_R_PTR; /* 0x047F SPC Read Pointer */
|
|
uint8_t RESERVED5[3]; /* 0x0480-0x0482 */
|
|
__IO uint8_t DATA_SC; /* 0x0483 Data Sequence Control */
|
|
uint8_t RESERVED6[0x28]; /* 0x0484-0x04AB */
|
|
__IO uint32_t TXRPT_START_OFFSET; /* 0x04AC TX Report Start Offset */
|
|
uint8_t RESERVED7[4]; /* 0x04B0-0x04B3 */
|
|
__IO uint32_t POWER_STAGE1; /* 0x04B4 Power Stage 1 */
|
|
__IO uint32_t POWER_STAGE2; /* 0x04B8 Power Stage 2 */
|
|
__IO uint32_t AMPDU_BURST_MODE; /* 0x04BC AMPDU Burst Mode */
|
|
__IO uint16_t PKT_VO_VI_LIFE_TIME; /* 0x04C0 Packet VO/VI Life Time */
|
|
__IO uint16_t PKT_BE_BK_LIFE_TIME; /* 0x04C2 Packet BE/BK Life Time */
|
|
__IO uint32_t STBC_SETTING; /* 0x04C4 STBC Setting */
|
|
__IO uint8_t HT_SINGLE_AMPDU; /* 0x04C7 HT Single AMPDU */
|
|
__IO uint32_t PROT_MODE_CTRL; /* 0x04C8 Protection Mode Control */
|
|
__IO uint16_t MAX_AGGR_NUM; /* 0x04CA Maximum Aggregation Number */
|
|
__IO uint8_t RTS_MAX_AGGR_NUM; /* 0x04CB RTS Maximum Aggregation Number */
|
|
__IO uint32_t BAR_MODE_CTRL; /* 0x04CC BAR Mode Control */
|
|
__IO uint8_t RA_TRY_RATE_AGG_LMT; /* 0x04CF RA Try Rate Aggregation Limit */
|
|
__IO uint32_t MACID_PKT_DROP0; /* 0x04D0 MACID Packet Drop 0 */
|
|
uint8_t RESERVED[0x2C]; /* 0x04D4-0x04FF */
|
|
} WIFI_PROT_TypeDef;
|
|
|
|
/* 0x0500h ~ 0x05FFh EDCA Configuration */
|
|
typedef struct {
|
|
__IO uint32_t VO_PARAM; /* 0x0500 EDCA VO parameter */
|
|
__IO uint32_t VI_PARAM; /* 0x0504 EDCA VI parameter */
|
|
__IO uint32_t BE_PARAM; /* 0x0508 EDCA BE parameter */
|
|
__IO uint32_t BK_PARAM; /* 0x050C EDCA BK parameter */
|
|
__IO uint32_t BCNTCFG; /* 0x0510 Beacon configuration */
|
|
__IO uint16_t PIFS; /* 0x0512 PIFS timing */
|
|
__IO uint8_t RDG_PIFS; /* 0x0513 RDG PIFS timing */
|
|
__IO uint16_t SIFS_CTX; /* 0x0514 SIFS context timing */
|
|
__IO uint16_t SIFS_TRX; /* 0x0516 SIFS TRX timing */
|
|
__IO uint16_t AGGR_BREAK_TIME; /* 0x051A Aggregation break time */
|
|
__IO uint8_t SLOT; /* 0x051B Slot time */
|
|
__IO uint32_t TX_PTCL_CTRL; /* 0x0520 TX protocol control */
|
|
__IO uint8_t TXPAUSE; /* 0x0522 TX pause */
|
|
__IO uint8_t DIS_TXREQ_CLR; /* 0x0523 Disable TX request clear */
|
|
__IO uint32_t RD_CTRL; /* 0x0524 RD control */
|
|
uint8_t RESERVED1[24]; /* 0x528-0x540 */
|
|
// Format for offset 540h-542h:
|
|
// [3:0]: TBTT prohibit setup in unit of 32us. The time for HW getting
|
|
// beacon content before TBTT. [7:4]: Reserved. [19:8]: TBTT
|
|
// prohibit hold in unit of 32us. The time for HW holding to send the beacon
|
|
// packet. [23:20]: Reserved
|
|
// Description:
|
|
// |
|
|
// |<--Setup--|--Hold------------>|
|
|
// --------------|----------------------
|
|
// |
|
|
// TBTT
|
|
// Note: We cannot update beacon content to HW or send any AC packets during
|
|
// the time between Setup and Hold. Described by Designer Tim and Bruce,
|
|
// 2011-01-14.
|
|
__IO uint32_t TBTT_PROHIBIT; /* 0x0540 TBTT prohibit */
|
|
__IO uint32_t RD_NAV_NXT; /* 0x0544 RD NAV next */
|
|
__IO uint16_t NAV_PROT_LEN; /* 0x0546 NAV protection length */
|
|
uint8_t RESERVED2[8]; /* 0x548-0x550 */
|
|
__IO uint8_t BCN_CTRL; /* 0x0550 Beacon control */
|
|
__IO uint8_t BCN_CTRL_1; /* 0x0551 Beacon control 1 */
|
|
__IO uint8_t MBID_NUM; /* 0x0552 MBID number */
|
|
__IO uint8_t DUAL_TSF_RST; /* 0x0553 Dual TSF reset */
|
|
__IO uint16_t BCN_INTERVAL; /* 0x0554 Beacon interval */
|
|
uint8_t RESERVED3[2]; /* 0x556-0x558 */
|
|
__IO uint8_t DRVERLYINT; /* 0x0558 Driver early interrupt */
|
|
__IO uint8_t BCNDMATIM; /* 0x0559 Beacon DMA timing */
|
|
__IO uint16_t ATIMWND; /* 0x055A ATIM window */
|
|
__IO uint16_t USTIME_TSF; /* 0x055C US time TSF */
|
|
__IO uint8_t BCN_MAX_ERR; /* 0x055D Beacon max error */
|
|
__IO uint8_t RXTSF_OFFSET_CCK; /* 0x055E RX TSF offset CCK */
|
|
__IO uint8_t RXTSF_OFFSET_OFDM; /* 0x055F RX TSF offset OFDM */
|
|
__IO uint32_t TSFTR; /* 0x0560 TSF timer */
|
|
uint8_t RESERVED4[14]; /* 0x564-0x572 */
|
|
__IO uint8_t CTWND; /* 0x0572 CT window */
|
|
__IO uint8_t BCNIVLCUNT; /* 0x0573 Beacon interval count */
|
|
uint8_t RESERVED5[3]; /* 0x574-0x577 */
|
|
__IO uint8_t SECONDARY_CCA_CTRL; /* 0x0577 Secondary CCA control */
|
|
uint8_t RESERVED6[8]; /* 0x578-0x580 */
|
|
__IO uint32_t PSTIMER; /* 0x0580 PS timer */
|
|
__IO uint32_t TIMER0; /* 0x0584 Timer 0 */
|
|
__IO uint32_t TIMER1; /* 0x0588 Timer 1 */
|
|
uint8_t RESERVED7[52]; /* 0x58C-0x5C0 */
|
|
__IO uint32_t ACMHWCTRL; /* 0x05C0 ACM hardware control */
|
|
uint8_t RESERVED8[52]; /* 0x5C4-0x5F8 */
|
|
__IO uint32_t SCH_TXCMD; /* 0x05F8 Schedule TX command */
|
|
uint8_t RESERVED9[4]; /* 0x5FC-0x600 */
|
|
} WIFI_EDCA_TypeDef;
|
|
|
|
/* 0x0600h ~ 0x07FFh WMAC Configuration */
|
|
typedef struct {
|
|
/* MAC Configuration (0x0600-0x060F) */
|
|
__IO uint32_t MAC_CR; /* 0x0600 MAC Configuration Register */
|
|
__IO uint32_t TCR; /* 0x0604 Transmission Configuration Register */
|
|
__IO uint32_t RCR; /* 0x0608 Receive Configuration Register */
|
|
__IO uint8_t RX_PKT_LIMIT; /* 0x060C RX Packet Limit */
|
|
__IO uint8_t RX_DLK_TIME; /* 0x060D RX Deadlock Time */
|
|
uint8_t RESERVED1[1]; /* 0x060E */
|
|
__IO uint8_t RX_DRVINFO_SZ; /* 0x060F RX Driver Info Size */
|
|
|
|
/* ID Configuration (0x0610-0x0628) */
|
|
__IO uint32_t MACID[2]; /* 0x0610 MAC ID */
|
|
__IO uint32_t BSSID[2]; /* 0x0618 BSSID */
|
|
__IO uint32_t MAR[2]; /* 0x0620 Multicast Address */
|
|
__IO uint32_t MBIDCAMCFG; /* 0x0628 MBSSID CAM Configuration */
|
|
|
|
uint8_t RESERVED2[12]; /* 0x062C-0x0637 */
|
|
|
|
/* Timing Configuration (0x0638-0x0642) */
|
|
__IO uint16_t USTIME_EDCA; /* 0x0638 US Time EDCA */
|
|
__IO uint16_t MAC_SPEC_SIFS; /* 0x063A MAC Specific SIFS */
|
|
__IO uint16_t RESP_SIFP_CCK; /* 0x063C Response SIFS CCK */
|
|
__IO uint16_t RESP_SIFS_OFDM; /* 0x063E Response SIFS OFDM */
|
|
__IO uint8_t ACKTO; /* 0x0640 ACK Timeout */
|
|
__IO uint8_t CTS2TO; /* 0x0641 CTS2 Timeout */
|
|
__IO uint16_t EIFS; /* 0x0642 Extended InterFrame Space */
|
|
|
|
uint8_t RESERVED3[13]; /* 0x0644-0x0650 */
|
|
|
|
/* Protocol Control (0x0652-0x0668) */
|
|
__IO uint16_t NAV_UPPER; /* 0x0652 NAV Upper (unit of 128) */
|
|
uint8_t RESERVED4[14]; /* 0x0654-0x0661 */
|
|
__IO uint16_t RTR; /* 0x0662 Response Time Report */
|
|
uint8_t RESERVED5[4]; /* 0x0664-0x0667 */
|
|
__IO uint32_t TRXPTCL_CTL; /* 0x0668 TRX Protocol Control */
|
|
|
|
uint8_t RESERVED6[4]; /* 0x066C-0x066F */
|
|
|
|
/* Security (0x0670-0x0680) */
|
|
__IO uint32_t CAMCMD; /* 0x0670 CAM Command */
|
|
__IO uint32_t CAMWRITE; /* 0x0674 CAM Write */
|
|
__IO uint32_t CAMREAD; /* 0x0678 CAM Read */
|
|
__IO uint32_t CAMDBG; /* 0x067C CAM Debug */
|
|
__IO uint32_t SECCFG; /* 0x0680 Security Configuration */
|
|
|
|
uint8_t RESERVED7[12]; /* 0x0684-0x068F */
|
|
|
|
/* Power Management (0x0690-0x06A8) */
|
|
__IO uint16_t WOW_CTRL; /* 0x0690 WoW Control */
|
|
__IO uint8_t PS_RX_INFO; /* 0x0692 Power Save RX Info */
|
|
__IO uint8_t UAPSD_TID; /* 0x0693 UAPSD TID */
|
|
uint8_t RESERVED8[4]; /* 0x0694-0x0697 */
|
|
__IO uint32_t WKFMCAM_CMD; /* 0x0698 Wake FM CAM Command */
|
|
__IO uint32_t WKFMCAM_RWD; /* 0x069C Wake FM CAM Read/Write Data */
|
|
__IO uint16_t RXFLTMAP0; /* 0x06A0 RX Filter Map 0 */
|
|
__IO uint16_t RXFLTMAP1; /* 0x06A2 RX Filter Map 1 */
|
|
__IO uint16_t RXFLTMAP2; /* 0x06A4 RX Filter Map 2 */
|
|
uint8_t RESERVED9[2]; /* 0x06A6-0x06A7 */
|
|
__IO uint32_t BCN_PSR_RPT; /* 0x06A8 Beacon Parser Report */
|
|
|
|
uint8_t RESERVED10[20]; /* 0x06AC-0x06BF */
|
|
|
|
/* Coexistence & Beamforming (0x06C0-0x06FC) */
|
|
__IO uint32_t BT_COEX_TABLE[9]; /* 0x06C0 BT Coexistence Table */
|
|
__IO uint32_t BFMER0_INFO[2]; /* 0x06E4 Beamformer 0 Information */
|
|
__IO uint32_t BFMER1_INFO[2]; /* 0x06EC Beamformer 1 Information */
|
|
__IO uint32_t CSI_RPT_PARAM_BW20; /* 0x06F4 CSI Report Parameter BW20 */
|
|
__IO uint32_t CSI_RPT_PARAM_BW40; /* 0x06F8 CSI Report Parameter BW40 */
|
|
__IO uint32_t CSI_RPT_PARAM_BW80; /* 0x06FC CSI Report Parameter BW80 */
|
|
|
|
/* Hardware Port 2 (0x0700-0x0718) */
|
|
__IO uint32_t MACID1[2]; /* 0x0700 MAC ID 1 */
|
|
__IO uint32_t BSSID1[2]; /* 0x0708 BSSID 1 */
|
|
uint8_t RESERVED11[4]; /* 0x0710-0x0713 */
|
|
__IO uint32_t BFMEE_SEL; /* 0x0714 Beamformee Selection */
|
|
__IO uint32_t SND_PTCL_CTRL; /* 0x0718 Sound Protocol Control */
|
|
} WIFI_WMAC_TypeDef;
|
|
|
|
typedef struct {
|
|
WIFI_SYS_TypeDef SYS; /* 0x0000-0x00FF */
|
|
WIFI_MAC_TypeDef MAC; /* 0x0100-0x01FF */
|
|
WIFI_TXDMA_TypeDef TXDMA; /* 0x0200-0x027F */
|
|
WIFI_RXDMA_TypeDef RXDMA; /* 0x0280-0x02FF */
|
|
WIFI_LXBUS_TypeDef LXBUS; /* 0x0300-0x03FF */
|
|
WIFI_PROT_TypeDef PROT; /* 0x0400-0x047F */
|
|
WIFI_EDCA_TypeDef EDCA; /* 0x0500-0x05FF */
|
|
WIFI_WMAC_TypeDef WMAC; /* 0x0600-0x07FF */
|
|
} WIFI_TypeDef;
|
|
|
|
/* Peripheral memory map */
|
|
#define SPI_FLASH_BASE 0x08000000
|
|
|
|
#define SYSTEM_CTRL_BASE 0x40000000
|
|
#define PERI_ON_BASE (SYSTEM_CTRL_BASE + 0x200)
|
|
|
|
#define NCO1_REG_BASE 0x40000080
|
|
#define BACKUP_REG_BASE 0x40000138
|
|
#define NCO2_REG_BASE 0x4000026C
|
|
|
|
#define GPIO_REG_BASE 0x40001000
|
|
#define TIMER_REG_BASE 0x40002000
|
|
#define VENDOR_REG_BASE 0x40002800
|
|
#define LOG_UART_REG_BASE 0x40003000
|
|
#define RTC_BASE 0x40003400
|
|
#define SPIC_CACHE_BASE 0x40003C00
|
|
#define ADC_REG_BASE 0x40010000
|
|
#define SPI_FLASH_CTRL_BASE 0x40020000
|
|
#define UART0_REG_BASE 0x40040000
|
|
#define UART1_REG_BASE 0x40040400
|
|
#define UART2_REG_BASE LOG_UART_REG_BASE
|
|
#define SPI0_REG_BASE 0x40042000
|
|
#define SPI1_REG_BASE 0x40042400
|
|
#define I2C0_REG_BASE 0x40044000
|
|
#define I2C1_REG_BASE 0x40044400
|
|
#define SDIO_DEVICE_REG_BASE 0x40050000
|
|
#define GDMA0_REG_BASE 0x40060000
|
|
#define GDMA1_REG_BASE 0x40061000
|
|
#define I2S0_REG_BASE 0x40062000
|
|
#define CRYPTO_REG_BASE 0x40070000
|
|
#define WIFI_REG_BASE 0x40080000
|
|
#define SIE_REG_BASE 0x400C0000
|
|
#define USOC_REG_BASE 0x400C2000
|
|
|
|
#define TIM0_BASE (TIMER_REG_BASE)
|
|
#define TIM1_BASE (TIMER_REG_BASE + 0x040)
|
|
#define TIM2_BASE (TIMER_REG_BASE + 0x080)
|
|
#define TIM3_BASE (TIMER_REG_BASE + 0x0C0)
|
|
#define TIM4_BASE (TIMER_REG_BASE + 0x100)
|
|
#define TIM5_BASE (TIMER_REG_BASE + 0x140)
|
|
|
|
/* Peripheral declaration */
|
|
// TODO: ida :)
|
|
// VENDOR_REG (base: 0x40002800)
|
|
// SDIO_DEVICE_REG (base: 0x40050000)
|
|
// WIFI_REG (base: 0x40080000)
|
|
// SIE_REG (base: 0x400C0000)
|
|
|
|
#define SYSTEM_CTRL ((SYSTEM_CTRL_TypeDef *)SYSTEM_CTRL_BASE)
|
|
#define PERI_ON ((PERI_ON_TypeDef *)PERI_ON_BASE)
|
|
|
|
#define GPIO ((GPIO_TypeDef *)(GPIO_REG_BASE))
|
|
#define GPIOA ((GPIO_Port_TypeDef *)(GPIO_REG_BASE + 0x00))
|
|
#define GPIOB ((GPIO_Port_TypeDef *)(GPIO_REG_BASE + 0x0C))
|
|
#define GPIOC ((GPIO_Port_TypeDef *)(GPIO_REG_BASE + 0x18))
|
|
|
|
#define UART0 ((UART_TypeDef *)UART0_REG_BASE)
|
|
#define UART1 ((UART_TypeDef *)UART1_REG_BASE)
|
|
#define UART2 ((UART_TypeDef *)LOG_UART_REG_BASE)
|
|
#define SPI0 ((SPI_TypeDef *)SPI0_REG_BASE)
|
|
#define SPI1 ((SPI_TypeDef *)SPI1_REG_BASE)
|
|
#define SPIC ((SPIC_TypeDef *)SPI_FLASH_CTRL_BASE)
|
|
#define ADC ((ADC_TypeDef *)ADC_REG_BASE)
|
|
#define I2C0 ((I2C_TypeDef *)I2C0_REG_BASE)
|
|
#define I2C1 ((I2C_TypeDef *)I2C1_REG_BASE)
|
|
#define GDMA0 ((GDMA_TypeDef *)GDMA0_REG_BASE)
|
|
#define GDMA1 ((GDMA_TypeDef *)GDMA1_REG_BASE)
|
|
#define I2S ((I2S_TypeDef *)I2S0_REG_BASE)
|
|
#define TIM0 ((RTIM_TypeDef *)TIM0_BASE)
|
|
#define TIM1 ((RTIM_TypeDef *)TIM1_BASE)
|
|
#define TIM2 ((RTIM_TypeDef *)TIM2_BASE)
|
|
#define TIM3 ((RTIM_TypeDef *)TIM3_BASE)
|
|
#define TIM4 ((RTIM_TypeDef *)TIM4_BASE)
|
|
#define TIM5 ((RTIM_TypeDef *)TIM5_BASE)
|
|
#define RTC ((RTC_TypeDef *)RTC_BASE)
|
|
#define IPSEC ((IPSEC_TypeDef *)CRYPTO_REG_BASE)
|
|
#define WIFI ((WIFI_TypeDef *)WIFI_REG_BASE)
|
|
#define USOC ((USOC_TypeDef *)USOC_REG_BASE)
|
|
#define NCO32k ((NCO32k_TypeDef *)NCO1_REG_BASE)
|
|
#define NCO8M ((NCO8M_TypeDef *)NCO2_REG_BASE)
|
|
#define BACKUP_REG ((BACKUP_REG_TypeDef *)BACKUP_REG_BASE)
|
|
#define SPIC_CACHE ((SPIC_CACHE_TypeDef *)SPIC_CACHE_BASE)
|
|
|
|
/* rtl8710b_backup_reg.h */
|
|
#define BKUP_BOR_DETECTION_EN (1 << 7) /* Enable BOR2 detection */
|
|
#define BKUP_BOR2_TEMP (1 << 6) /* BOR2 HW temp bit */
|
|
#define BKUP_SYS_RESET_FLAG (1 << 5) /* System reset indicator */
|
|
#define BKUP_UART_DEBUG_FLAG (1 << 4) /* UART download debug flag */
|
|
#define BKUP_UART_BOOT_FLAG (1 << 3) /* UART download flag */
|
|
#define BKUP_RTC_RESTORE_FLAG (1 << 2) /* RTC init flag */
|
|
#define BKUP_BOR2_RESET_FLAG (1 << 1) /* BOR2 reset indicator */
|
|
#define BKUP_CPU_RESET_FLAG (1 << 0) /* CPU/Watchdog reset indicator */
|
|
|
|
#define BKUP_RTC_BACKUP_MASK (0xFF << 8) /* RTC backup mask */
|
|
#define BKUP_SYSTEM_RESERVED_MASK (0xFF) /* System reserved bits mask */
|
|
|
|
#define BKUP_GET_RTC_BACKUP(reg) (((reg)->DWORD[0] & BKUP_RTC_BACKUP_MASK) >> 8)
|
|
#define BKUP_SET_RTC_BACKUP(reg, val) \
|
|
((reg)->DWORD[0] = ((reg)->DWORD[0] & ~BKUP_RTC_BACKUP_MASK) | \
|
|
(((uint32_t)(val) << 8) & BKUP_RTC_BACKUP_MASK))
|
|
|
|
/* rtl8710b_clk.h */
|
|
/* Clock source position and mask */
|
|
#define CPU_CLK_POS 4
|
|
|
|
/* Clock freq set macro */
|
|
#define SET_CPU_CLOCK(source) \
|
|
(SYSTEM_CTRL->CLK_CTRL1 = \
|
|
(SYSTEM_CTRL->CLK_CTRL1 & ~SYS_CLK_CPU_CLK_SEL) | (source))
|
|
|
|
/* Clock sources - values pre-shifted to position */
|
|
#define CPU_CLK_125M (0 << CPU_CLK_POS)
|
|
#define CPU_CLK_62_5M (1 << CPU_CLK_POS)
|
|
#define CPU_CLK_31_25M (2 << CPU_CLK_POS)
|
|
#define CPU_CLK_16_625M (3 << CPU_CLK_POS)
|
|
#define CPU_CLK_XTAL (4 << CPU_CLK_POS)
|
|
#define CPU_CLK_ANA_4M (5 << CPU_CLK_POS)
|
|
|
|
/* NCO32k (NCO1) CLK_INFO Register Bits */
|
|
#define NCO1_CLK_INFO_FREQ_MASK 0x00FFFFFF /* Unregulated clock freq */
|
|
#define NCO1_CLK_INFO_32K_RDY (1 << 24) /* 32K clock output rdy */
|
|
#define NCO1_CLK_INFO_CAL_RDY (1 << 25) /* 32K calibration rdy */
|
|
|
|
/* NCO32k (NCO1) CTRL Register Bits */
|
|
#define NCO1_REF_FREQ_MASK 0x000003FF /* Reference clock freq mask */
|
|
#define NCO1_32K_EN (1 << 16) /* 32K clock output enable */
|
|
#define NCO1_REF_EN (1 << 17) /* Reference clock enable */
|
|
#define NCO1_CAL_CYCLES (0xF << 20) /* num of cycles used during cali */
|
|
#define NCO1_THRESH_MASK (0x7F << 24) /* 32K threshold */
|
|
|
|
/* NCO2 Control Register Bits */
|
|
#define NCO2_OUT_EN (1 << 0) /* Enable NCO2 clock output */
|
|
|
|
/* System Clock Control Registers (SYS_CLK_CTRL0) */
|
|
#define SYS_CLK_IOBUS_EN (1 << 2) /* Enable IO bus clock */
|
|
#define SYS_CLK_EELDR_EN (1 << 1) /* Enable EELDR clock */
|
|
#define SYS_CLK_SYSREG_EN (1 << 0) /* Enable system register clock */
|
|
|
|
/* SYS_CLK_CTRL1 */
|
|
#define SYS_CLK_EXT32K_SEL (1 << 8) /* Select external 32KHz clock */
|
|
#define SYS_CLK_CPU_CLK_SEL (7 << CPU_CLK_POS) /* CPU clock selection mask */
|
|
#define SYS_CLK_EELDR_SEL (1 << 0) /* EELDR clock selection */
|
|
|
|
/* Crystal Control Register 0 (XTAL_CTRL0) */
|
|
#define XTAL_EN (1 << 1) /* Crystal oscillator enable */
|
|
#define XTAL_BGMB_EN (1 << 0) /* Bandgap bias enable */
|
|
/* 1: Gate PLL reference clock from XTAL; 0: not gated */
|
|
#define XTAL_GSPL_EN (1 << 4)
|
|
#define XTAL_GMP_MASK (0x1F << 8) /* Crystal GM-P control */
|
|
#define XTAL_GMN_MASK (0x1F << 13) /* Crystal GM-N control */
|
|
#define XTAL_SC_XI_MASK (0x3F << 18) /* Crystal input scaling */
|
|
#define XTAL_SC_XO_MASK (0x3F << 24) /* Crystal output scaling */
|
|
#define XTAL_GATED_OK (1 << 30) /* Crystal gating status */
|
|
#define XTAL_XQSEL_RF (1 << 31) /* RF crystal quality selection */
|
|
|
|
/* Crystal Control Register 1 (XTAL_CTRL1) */
|
|
#define XTAL_DELAY_SYSPLL (1 << 25) /* System PLL delay enable */
|
|
#define XTAL_DELAY_USB (1 << 24) /* USB delay enable */
|
|
#define XTAL_DELAY_WLAFE (1 << 23) /* WLAN AFE delay enable */
|
|
/* Automatic amplitude control GM enable */
|
|
#define XTAL_AAC_GM_EN (1 << 21)
|
|
#define XTAL_AAC_PEAKDET_EN (1 << 20) /* Peak detector enable */
|
|
#define XTAL_AGPIO_MASK (1 << 17) /* GPIO control mask */
|
|
/* System PLL driver strength */
|
|
#define XTAL_DRV_SYSPLL_MASK (0x3 << 15)
|
|
#define XTAL_GATE_SYSPLL (1 << 14) /* System PLL clock gating */
|
|
#define XTAL_DRV_USB_MASK (0x3 << 12) /* USB driver strength */
|
|
#define XTAL_GATE_USB (1 << 11) /* USB clock gating */
|
|
#define XTAL_DRV_WLAFE_MASK (0x3 << 9) /* WLAN AFE driver strength */
|
|
#define XTAL_GATE_WLAFE (1 << 8) /* WLAN AFE clock gating */
|
|
#define XTAL_DRV_RF2_MASK (0x3 << 6) /* RF2 driver strength */
|
|
#define XTAL_GATE_RF2 (1 << 5) /* RF2 clock gating */
|
|
#define XTAL_DRV_RF1_MASK (0x3 << 3) /* RF1 driver strength */
|
|
#define XTAL_GATE_RF1 (1 << 2) /* RF1 clock gating */
|
|
#define XTAL_LDO_MASK (0x3 << 0) /* LDO control mask */
|
|
|
|
/* System PLL Control Register 0 (SYSPLL_CTRL0) */
|
|
#define SYSPLL_CKTST_EN (1 << 22) /* Clock test enable */
|
|
#define SYSPLL_MONCK_SEL_MASK (0x7 << 19) /* Monitor clock selection */
|
|
#define SYSPLL_CP_IOFFSET_MASK (0x1F << 14) /* Charge pump current offset */
|
|
#define SYSPLL_FREF_EDGE (1 << 9) /* Reference clock edge selection */
|
|
#define SYSPLL_EN (1 << 1) /* PLL enable */
|
|
#define SYSPLL_LVPC_EN (1 << 0) /* Low voltage PLL core enable */
|
|
|
|
/* System PLL Control Register 1 (SYSPLL_CTRL1) */
|
|
/* Clock selection: 1=200MHz, 0=166.666MHz */
|
|
#define SYSPLL_CL200M_SEL (1 << 17)
|
|
#define SYSPLL_CK500K_SEL (1 << 15) /* Clock source: 1=external, 0=PLL */
|
|
#define SYSPLL_CK200M_EN (1 << 14) /* 200MHz clock enable */
|
|
#define SYSPLL_CKSDR_EN (1 << 13) /* SDRAM clock enable */
|
|
/* SDRAM clock divider: 00=off, 01=25MHz, 10=50MHz, 11=100MHz */
|
|
#define SYSPLL_CKSDR_DIV_MASK (0x3 << 11)
|
|
#define SYSPLL_CK24P576_EN (1 << 10) /* 24.576MHz clock enable */
|
|
#define SYSPLL_CK22P5792_EN (1 << 9) /* 22.5792MHz clock enable */
|
|
#define SYSPLL_CK83P33M_EN (1 << 8) /* 83.33MHz clock enable */
|
|
#define SYSPLL_PS_EN (1 << 7) /* Phase shift enable */
|
|
/**
|
|
* Clock phase selection when reg_ps_enb:
|
|
* 000/001.../111 corresponds to phases: 0°, 45°...315°
|
|
*/
|
|
#define SYSPLL_PS_SEL_MASK (0x7 << 4)
|
|
|
|
/* System PLL Control Register 2 (SYSPLL_CTRL2) */
|
|
#define SYSPLL_ADC_EN (1 << 25) /* ADC PLL enable */
|
|
|
|
/* System PLL Control Register 3 (SYSPLL_CTRL3) */
|
|
/* 500MHz clock divider: period = (value + 2) cycles */
|
|
#define SYSPLL_DIV_MASK (0x1FF << 6)
|
|
/* Phase selection for 500MHz clock:
|
|
* 0=0°, 1=45°, 2=90°, 3=135°
|
|
* 4=180°, 5=225°, 6=270°, 7=315° */
|
|
#define SYSPLL_PHASE_MASK (0x7 << 3)
|
|
#define SYSPLL_500M_PS_EN (1 << 2) /* Enable 500MHz phase-shifted clock */
|
|
#define SYSPLL_500M_EN (1 << 1) /* Enable 500MHz clock (HW auto-enabled) */
|
|
|
|
/* 32KHz Oscillator Control Register (OSC32K_CTRL) */
|
|
#define OSC32K_CKGEN_EN (1 << 0) /* Enable 32KHz clock generator */
|
|
/* Calibration mode select:
|
|
* 1=New (REGUOUT=OSCIN=8MHz)
|
|
* 0=Original (REGUOUT=OSCIN=32KHz) */
|
|
#define OSC32K_CAL_MODE (1 << 1)
|
|
#define OSC32K_COMP_RES_MASK (0x3 << 2) /* Compensation resistor control */
|
|
#define OSC32K_8M_EN (1 << 4) /* Enable 8MHz oscillator clock */
|
|
#define OSC32K_FREF_EN (1 << 5) /* Enable 25MHz reference clock */
|
|
#define OSC32K_BIAS_MASK (0xFFFF << 16) /* Bias current control */
|
|
|
|
/* 32KHz Oscillator Register Control 0 (OSC32K_REG_CTRL0) */
|
|
#define OSC32K_CMD_WRITE (1 << 23) /* Command type: 1=Write, 0=Read */
|
|
#define OSC32K_ADDR_MASK (0x3F << 16) /* Register address */
|
|
#define OSC32K_WDATA_MASK (0xFFFF << 0) /* Write data */
|
|
|
|
/* 32KHz Oscillator Register Control 1 (OSC32K_REG_CTRL1) */
|
|
#define OSC32K_RDATA_MASK (0xFFFF << 0) /* Indirect read data */
|
|
|
|
/* rtl8711b_syscfg.h */
|
|
/* SYSCFG Register Definitions */
|
|
|
|
/* EFUSE_SYSCFG0 Register */
|
|
/* [29:24] EEROM SWR Parameter [5:0] */
|
|
#define SYSCFG0_EEROM_SWR_PAR_MASK (0x3F << 24)
|
|
/* [23:20] EEROM LDO Parameter [7:4] */
|
|
#define SYSCFG0_EEROM_LDO_PAR_MASK (0x0F << 20)
|
|
#define SYSCFG0_CHIPPDN_EN (1 << 17) /* Reset pin power down control */
|
|
#define SYSCFG0_EEROM_B12V_EN (1 << 16) /* EEROM B12V enable */
|
|
#define SYSCFG0_EEROM_VID1_MASK (0xFF << 8) /* [15:8] EEROM VID1 */
|
|
#define SYSCFG0_EEROM_VID0_MASK 0xFF /* [7:0] EEROM VID0 */
|
|
|
|
/* EFUSE_SYSCFG1 Register */
|
|
#define SYSCFG1_PDSPL_STL_MASK (0x03 << 24) /* [25:24] PDSPL STL */
|
|
#define SYSCFG1_PDSOC_STL_MASK (0x03 << 22) /* [23:22] PDSOC STL */
|
|
#define SYSCFG1_PDPON_STL_MASK (0x03 << 20) /* [21:20] PDPON STL */
|
|
#define SYSCFG1_SWREG_XRT_MASK (0x03 << 18) /* [19:18] SWREG XRT */
|
|
#define SYSCFG1_SWSLC_STL_MASK (0x03 << 16) /* [17:16] SWSLC STL */
|
|
/* [15:14] SWR Parameter [46:45] */
|
|
#define SYSCFG1_SWR_PAR_46_45_MASK (0x03 << 14)
|
|
/* [13:12] SWR Parameter [40:39] */
|
|
#define SYSCFG1_SWR_PAR_40_39_MASK (0x03 << 12)
|
|
/* [11:4] SWR Parameter [33:26] */
|
|
#define SYSCFG1_SWR_PAR_33_26_MASK (0xFF << 4)
|
|
/* [2:0] SWSLD Volume */
|
|
#define SYSCFG1_SWSLD_VOL_MASK 0x07
|
|
|
|
/* EFUSE_SYSCFG2 Register */
|
|
/* [30:21] ANAPAR SPLL [24:15] */
|
|
#define SYSCFG2_ANAPAR_SPLL_24_15_MASK (0x3FF << 21)
|
|
/* [19:16] ANAPAR SPLL [5:2] */
|
|
#define SYSCFG2_ANAPAR_SPLL_05_02_MASK (0x0F << 16)
|
|
/* [13:12] XTAL STEL Select */
|
|
#define SYSCFG2_XTAL_STEL_SEL_MASK (0x03 << 12)
|
|
/* [11:8] XTAL Frequency Select */
|
|
#define SYSCFG2_XTAL_FREQ_SEL_MASK (0x0F << 8)
|
|
|
|
/* SYSTEM_CFG0 Register */
|
|
#define SYSCFG0_RF_RL_ID_MASK 0x0F /* [3:0] RF Vendor ID */
|
|
#define SYSCFG0_CUT_VER_MASK (0x0F << 4) /* [7:4] Cut Version */
|
|
#define SYSCFG0_VENDOR_ID_MASK (0x0F << 8) /* [11:8] Vendor ID */
|
|
#define SYSCFG0_CHIP_TYPE_MASK (1 << 16) /* Chip Type */
|
|
#define SYSCFG0_BD_OPT_MASK (0x0F << 24) /* [27:24] Board Option */
|
|
#define SYSCFG0_BD_PKG_SEL (1 << 31) /* Board Package Select */
|
|
|
|
/* SYSTEM_CFG1 Register */
|
|
#define SYSCFG1_TRP_ICFG_MASK (0x0F << 28) /* [31:28] TRP ICFG */
|
|
#define SYSCFG1_TRP_UART_IMAGE (1 << 27) /* TRP UART Image */
|
|
#define SYSCFG1_TRP_SPSLDO_SEL (1 << 25) /* TRP SPSLDO Select */
|
|
#define SYSCFG1_V15_VLD (1 << 16) /* V15 Valid */
|
|
#define SYSCFG1_SYSPLL_CLK_RDY (1 << 9) /* System PLL Clock Ready */
|
|
#define SYSCFG1_XCLK_VLD (1 << 8) /* XCLK Valid */
|
|
#define SYSCFG1_ALDN_STS (1 << 0) /* ALDN Status */
|
|
|
|
/* rtl8711b_peri_on.h */
|
|
// 2 0x200 REG_PEON_PWR_CTRL
|
|
#define BIT_SOC_UAHV_EN (1 << 2)
|
|
#define BIT_SOC_UALV_EN (1 << 1)
|
|
#define BIT_SOC_USBD_EN (1 << 0)
|
|
|
|
// 2 0x210 REG_SOC_FUNC_EN
|
|
#define BIT_SOC_BOOT_FROM_JTAG (1 << 31)
|
|
#define BIT_SOC_UNLOCK_FROM_JTAG (1 << 30)
|
|
#define BIT_SOC_WAKE_FROM_PS (1 << 29)
|
|
#define BIT_SOC_PATCH_FUNC0 (1 << 28)
|
|
#define BIT_SOC_PATCH_FUNC1 (1 << 27)
|
|
#define BIT_SOC_PATCH_FUNC2 (1 << 26)
|
|
|
|
#define BIT_SOC_XMODEM_PAGE_PG (1 << 25)
|
|
#define BIT_SOC_XMODEM_FLASH_EMPTY (1 << 24)
|
|
|
|
#define BIT_SOC_SECURITY_ENGINE_EN (1 << 20)
|
|
#define BIT_SOC_GTIMER_EN (1 << 16)
|
|
#define BIT_SOC_GDMA1_EN (1 << 14)
|
|
#define BIT_SOC_GDMA0_EN (1 << 13)
|
|
#define BIT_SOC_LOG_UART_EN (1 << 12)
|
|
#define BIT_SOC_CPU_EN (1 << 8)
|
|
#define BIT_SOC_MEM_CTRL_EN (1 << 6)
|
|
#define BIT_SOC_FLASH_EN (1 << 4)
|
|
#define BIT_SOC_LXBUS_EN (1 << 2)
|
|
#define BIT_SOC_OCP_EN (1 << 1)
|
|
#define BIT_SOC_FUN_EN (1 << 0)
|
|
|
|
// 2 0x0214 REG_SOC_HCI_COM_FUNC_EN
|
|
#define BIT_SOC_HCI_WL_MACON_EN (1 << 16)
|
|
#define BIT_SOC_HCI_SM_SEL (1 << 13)
|
|
#define BIT_SOC_HCI_OTG_RST_MUX (1 << 5)
|
|
#define BIT_SOC_HCI_OTG_EN (1 << 4)
|
|
#define BIT_SOC_HCI_SDIOD_ON_RST_MUX (1 << 3)
|
|
#define BIT_SOC_HCI_SDIOD_OFF_EN (1 << 1)
|
|
#define BIT_SOC_HCI_SDIOD_ON_EN (1 << 0)
|
|
|
|
// 2 0x0218 REG_SOC_PERI_FUNC0_EN
|
|
#define BIT_PERI_I2S0_EN (1 << 24)
|
|
#define BIT_PERI_I2C1_EN (1 << 17)
|
|
#define BIT_PERI_I2C0_EN (1 << 16)
|
|
#define BIT_PERI_SPI1_EN (1 << 9)
|
|
#define BIT_PERI_SPI0_EN (1 << 8)
|
|
#define BIT_PERI_UART2_EN (1 << 2)
|
|
#define BIT_PERI_UART1_EN (1 << 1)
|
|
#define BIT_PERI_UART0_EN (1 << 0)
|
|
|
|
// 2 0x021C REG_SOC_PERI_FUNC1_EN
|
|
#define BIT_PERI_GPIO_EN (1 << 8)
|
|
#define BIT_PERI_ADC0_EN (1 << 0)
|
|
|
|
// 2 0x0220 REG_SOC_PERI_BD_FUNC0_EN
|
|
#define BIT_PERI_UART2_BD_EN (1 << 2)
|
|
#define BIT_PERI_UART1_BD_EN (1 << 1)
|
|
#define BIT_PERI_UART0_BD_EN (1 << 0)
|
|
|
|
// 2 0x0230 REG_PESOC_CLK_CTRL
|
|
#define BIT_SOC_SLPCK_BTCMD_EN (1 << 29)
|
|
#define BIT_SOC_ACTCK_BTCMD_EN (1 << 28)
|
|
#define BIT_SOC_ACTCK_GPIO_EN (1 << 24)
|
|
#define BIT_SOC_ACTCK_GDMA1_EN (1 << 18)
|
|
#define BIT_SOC_ACTCK_GDMA0_EN (1 << 16)
|
|
#define BIT_SOC_ACTCK_TIMER_EN (1 << 14)
|
|
#define BIT_SOC_ACTCK_LOG_UART_EN (1 << 12)
|
|
#define BIT_SOC_ACTCK_FLASH_EN (1 << 8)
|
|
#define BIT_SOC_ACTCK_VENDOR_REG_EN (1 << 6)
|
|
#define BIT_SOC_ACTCK_TRACE_EN (1 << 4)
|
|
#define BIT_SOC_CKE_PLFM (1 << 2)
|
|
#define BIT_SOC_CKE_OCP (1 << 0)
|
|
|
|
// 2 0x0234 REG_PESOC_PERI_CLK_CTRL0
|
|
#define BIT_SOC_ACTCK_SPI1_EN (1 << 18)
|
|
#define BIT_SOC_ACTCK_SPI0_EN (1 << 16)
|
|
#define BIT_SOC_ACTCK_UART1_EN (1 << 2)
|
|
#define BIT_SOC_ACTCK_UART0_EN (1 << 0)
|
|
|
|
// 2 0x0238 REG_PESOC_PERI_CLK_CTRL1
|
|
#define BIT_SOC_ACTCK_ADC_EN (1 << 24)
|
|
#define BIT_SOC_ACTCK_I2S_EN (1 << 16)
|
|
#define BIT_SOC_ACTCK_I2C1_EN (1 << 2)
|
|
#define BIT_SOC_ACTCK_I2C0_EN (1 << 0)
|
|
|
|
// 2 0x0240 REG_PESOC_HCI_CLK_CTRL0
|
|
#define BIT_SOC_ACTCK_OTG_EN (1 << 4)
|
|
#define BIT_SOC_ACTCK_SDIO_HST_EN \
|
|
(1 << 2) // SDIO_HST clock enable in CPU run mode
|
|
#define BIT_SOC_ACTCK_SDIO_DEV_EN \
|
|
(1 << 0) // SDIO_DEV clock enable in CPU run mode
|
|
|
|
/* REG_PESOC_CLK_SEL 0x0250 */
|
|
#define BIT_SHIFT_PESOC_UART1_SCLK_SEL 26
|
|
/* [27:26] uart1 rx clock, 01: osc 8m; 00: xtal; 10: xtal nco */
|
|
#define BIT_MASK_PESOC_UART1_SCLK_SEL 0x03
|
|
#define BIT_SHIFT_PESOC_UART0_SCLK_SEL 19
|
|
/* [20:19] uart0 rx clock, 01: osc 8m; 00: xtal; 10: xtal nco */
|
|
#define BIT_MASK_PESOC_UART0_SCLK_SEL 0x03
|
|
|
|
/* 1: enable to generate flash clock (with phase shift) divided by 500M pll
|
|
* clock, HW detect this signal's rising edge to start the phase shift clock
|
|
* division circuit. */
|
|
#define BIT_FLASH_CK_PS_DIV_EN (1 << 25)
|
|
/* 1: enable to generate flash clock (no phase shift) divided by 500M pll clock,
|
|
* HW detect this signal's rising edge to start the no phase shift division
|
|
* circuit. */
|
|
#define BIT_FLASH_CK_DIV_EN (1 << 24)
|
|
/* 1: delay flash sout for calibration; 0: bypass flash sout to spic */
|
|
#define BIT_FLASH_CAL_EN (1 << 23)
|
|
#define BIT_SHIFT_FLASH_CK_PS_INT 12
|
|
/* [14:12] Flash clock phase shift in units of 500M pll clock cycels */
|
|
#define BIT_MASK_FLASH_CK_PS_INT 0x03
|
|
/* ready flag of Flash clock with phase shift, Read only */
|
|
#define BIT_FLASH_PS_DIV_RDY (1 << 7)
|
|
/* ready flag of Flash clock, Read only */
|
|
#define BIT_FLASH_DIV_RDY (1 << 6)
|
|
#define BIT_SHIFT_PESOC_TRACE_CK_SEL 4
|
|
/* [5:4] "Trace clock select0: 12.5MH1: 25MHz2: 50MHz3: 100MHz" */
|
|
#define BIT_MASK_PESOC_TRACE_CK_SEL 0x03
|
|
/* "Only valid when r_FLASH_DIV_FRAC= 1, it decides the duty cycle of flash
|
|
* clock when not divided by integer1: duty cycle > 50% ; 0: duty cycle < 50%"
|
|
*/
|
|
#define BIT_FLASH_DIV_HIGH_FRAC (1 << 3)
|
|
/* "Flash clock division ratio, fractional part0: no fraction, only divided by
|
|
* integer set by bit[1:0], 1: 0.5" */
|
|
#define BIT_FLASH_DIV_FRAC (1 << 2)
|
|
#define BIT_SHIFT_DIV_INT 0
|
|
/* [1:0] "Flash clock division ratio, integrate part0: divided by 21: divided by
|
|
* 32: divided by 43: divided by 5" */
|
|
#define BIT_MASK_FLASH_DIV_INT 0x03
|
|
|
|
// 0x0244 REG_PESOC_COM_CLK_CTRL1
|
|
#define BIT_SOC_ACTCK_SECURITY_ENG_EN (1 << 4)
|
|
// spec name is wrong (BIT_SOC_ACTCK_WL_EN)
|
|
#define BIT_SOC_ACTCK_LXBUS_EN (1 << 0)
|
|
|
|
// 0x02E0 REG_PON_PINMUX_CTRL
|
|
#define BIT_HCI_SDIOD_PIN_EN (1 << 0)
|
|
|
|
// 0x0304 REG_PESOC_SOC_CTRL
|
|
#define BIT_PESOC_LX_SLV_SWAP_SEL (1 << 10)
|
|
#define BIT_PESOC_LX_MST_SWAP_SEL (1 << 9)
|
|
#define BIT_PESOC_LX_WL_SWAP_SEL (1 << 8)
|
|
|
|
// 0x2FC REG_FW_PPROTECT_KEY_CTRL
|
|
#define BIT_RDP_EN (1 << 3) /* load from efuse */
|
|
#define BIT_RDP_EN_LOAD (1 << 2)
|
|
#define BIT_RDP_KEY_REQ (1 << 1)
|
|
#define BIT_OTF_KEY_REQ (1 << 0)
|
|
|
|
/* rtl8711b_pinmux.h */
|
|
#define _PA_0 (0x00)
|
|
#define _PA_1 (0x01)
|
|
#define _PA_2 (0x02)
|
|
#define _PA_3 (0x03)
|
|
#define _PA_4 (0x04)
|
|
#define _PA_5 (0x05)
|
|
#define _PA_6 (0x06)
|
|
#define _PA_7 (0x07)
|
|
#define _PA_8 (0x08)
|
|
#define _PA_9 (0x09)
|
|
#define _PA_10 (0x0A)
|
|
#define _PA_11 (0x0B)
|
|
#define _PA_12 (0x0C)
|
|
#define _PA_13 (0x0D)
|
|
#define _PA_14 (0x0E)
|
|
#define _PA_15 (0x0F)
|
|
#define _PA_16 (0x10)
|
|
#define _PA_17 (0x11)
|
|
#define _PA_18 (0x12)
|
|
#define _PA_19 (0x13)
|
|
#define _PA_20 (0x14)
|
|
#define _PA_21 (0x15)
|
|
#define _PA_22 (0x16)
|
|
#define _PA_23 (0x17)
|
|
#define _PA_24 (0x18)
|
|
#define _PA_25 (0x19)
|
|
#define _PA_26 (0x1A)
|
|
#define _PA_27 (0x1B)
|
|
#define _PA_28 (0x1C)
|
|
#define _PA_29 (0x1D)
|
|
#define _PA_30 (0x1E)
|
|
#define _PA_31 (0x1F)
|
|
#define _PB_0 (0x20)
|
|
#define _PB_1 (0x21)
|
|
#define _PB_2 (0x22)
|
|
#define _PB_3 (0x23)
|
|
#define _PB_4 (0x24)
|
|
#define _PB_5 (0x25)
|
|
#define _PB_6 (0x26)
|
|
#define _PB_7 (0x27)
|
|
#define _PB_8 (0x28)
|
|
#define _PNC (0xFFFFFFFF)
|
|
|
|
// PINMUX function modes
|
|
#define PINMUX_FN_GPIO 0x100 // Normal GPIO mode
|
|
#define PINMUX_FN_UART 0x101 // UART function
|
|
#define PINMUX_FN_SPIM 0x102 // SPI1 function (why diff function code?)
|
|
#define PINMUX_FN_SPIS 0x103 // SPI0 function
|
|
#define PINMUX_FN_SPIF 0x104 // SPI Flash interface
|
|
#define PINMUX_FN_I2C 0x105 // I2C function
|
|
#define PINMUX_FN_SDIO 0x106 // SDIO function
|
|
#define PINMUX_FN_PWM 0x107 // PWM
|
|
#define PINMUX_FN_TIMINPUT 0x107 // PWM
|
|
#define PINMUX_FN_SWD 0x108 // SWD/JTAG function
|
|
#define PINMUX_FN_EXT32K 0x108
|
|
#define PINMUX_FN_RTCOUT 0x108
|
|
#define PINMUX_FN_I2S 0x109 // I2S function
|
|
#define PINMUX_FN_COEX_EXT32K 0x10a
|
|
#define PINMUX_FN_BTCOEX 0x10a
|
|
#define PINMUX_FN_WLLED 0x10a
|
|
|
|
#define PAD_DRV_STRENGTH_0 (0x00000000 << 9)
|
|
#define PAD_DRV_STRENGTH_1 (0x00000001 << 9)
|
|
#define PAD_DRV_STRENGTH_2 (0x00000002 << 9)
|
|
#define PAD_DRV_STRENGTH_3 (0x00000003 << 9)
|
|
#define PAD_DRV_STRENGTH_4 (0x00000004 << 9)
|
|
#define PAD_DRV_STRENGTH_5 (0x00000005 << 9)
|
|
#define PAD_DRV_STRENGTH_6 (0x00000006 << 9)
|
|
#define PAD_DRV_STRENGTH_7 (0x00000007 << 9)
|
|
|
|
#define PINMUX_GET_REG_SHIFT(pin, reg, shift) \
|
|
volatile uint32_t *reg = &PERI_ON->GPIO_PINMUX_CTRL[pin >> 1]; \
|
|
uint32_t shift = (pin & 1) << 4
|
|
|
|
static inline void PINMUX_ConfigMasked(uint32_t pin, uint32_t value,
|
|
uint32_t mask) {
|
|
PINMUX_GET_REG_SHIFT(pin, reg, shift);
|
|
*reg = (*reg & ~(mask << shift)) | (value << shift);
|
|
}
|
|
|
|
static inline void PINMUX_ConfigFn(uint32_t pin, uint32_t func) {
|
|
PINMUX_ConfigMasked(pin, func, 0xFFFF);
|
|
}
|
|
|
|
static inline void PINMUX_ConfigPadPull(uint8_t pin, uint8_t pull_type) {
|
|
PINMUX_ConfigMasked(pin, pull_type, 0xC0U);
|
|
}
|
|
|
|
static inline void PINMUX_Config(uint32_t pin, uint32_t func,
|
|
uint8_t pull_type) {
|
|
PINMUX_ConfigMasked(pin, func | ((uint32_t)pull_type << 6), 0xFFFF);
|
|
}
|
|
|
|
/* rtl8711b_gpio.h */
|
|
|
|
/* GPIO_Pull_parameter_definitions */
|
|
#define GPIO_PuPd_NOPULL 0x00 // 00
|
|
#define GPIO_PuPd_SHUTDOWN 0x00 // 00
|
|
#define GPIO_PuPd_DOWN 0x80 // 10
|
|
#define GPIO_PuPd_UP 0x40 // 01
|
|
|
|
/* GPIO_INT_Trigger_parameter_definitions */
|
|
#define GPIO_INT_Trigger_LEVEL 0x0 /*This interrupt is level trigger */
|
|
#define GPIO_INT_Trigger_EDGE 0x1 /*This interrupt is edge trigger */
|
|
|
|
#define IS_GPIOIT_LEVEL_TYPE(TYPE) \
|
|
(((TYPE) == GPIO_INT_Trigger_LEVEL) || ((TYPE) == GPIO_INT_Trigger_EDGE))
|
|
|
|
/* GPIO_INT_Polarity_parameter_definitions */
|
|
/*Setting interrupt to low active: falling edge or low level */
|
|
#define GPIO_INT_POLARITY_ACTIVE_LOW 0x0
|
|
/*Setting interrupt to high active: rising edge or high level */
|
|
#define GPIO_INT_POLARITY_ACTIVE_HIGH 0x1
|
|
|
|
#define IS_GPIOIT_POLARITY_TYPE(TYPE) \
|
|
(((TYPE) == GPIO_INT_POLARITY_ACTIVE_LOW) || \
|
|
((TYPE) == GPIO_INT_POLARITY_ACTIVE_HIGH))
|
|
|
|
/* GPIO_INT_Debounce_parameter_definitions */
|
|
#define GPIO_INT_DEBOUNCE_DISABLE 0x0 /*Disable interrupt debounce */
|
|
#define GPIO_INT_DEBOUNCE_ENABLE 0x1 /*Enable interrupt debounce */
|
|
|
|
#define IS_GPIOIT_DEBOUNCE_TYPE(TYPE) \
|
|
(((TYPE) == GPIO_INT_DEBOUNCE_DISABLE) || \
|
|
((TYPE) == GPIO_INT_DEBOUNCE_ENABLE))
|
|
|
|
/* rtl8711b_rcc.h */
|
|
|
|
/* 0x230 REG_PESOC_CLK_CTRL */
|
|
#define APBPeriph_GPIO_CLOCK (BIT_SOC_ACTCK_GPIO_EN)
|
|
#define APBPeriph_GDMA1_CLOCK (BIT_SOC_ACTCK_GDMA1_EN)
|
|
#define APBPeriph_GDMA0_CLOCK (BIT_SOC_ACTCK_GDMA0_EN)
|
|
#define APBPeriph_GTIMER_CLOCK (BIT_SOC_ACTCK_TIMER_EN)
|
|
#define APBPeriph_LOGUART_CLOCK (BIT_SOC_ACTCK_LOG_UART_EN)
|
|
#define APBPeriph_FLASH_CLOCK (BIT_SOC_ACTCK_FLASH_EN)
|
|
#define APBPeriph_VENDOR_REG_CLOCK (BIT_SOC_ACTCK_VENDOR_REG_EN)
|
|
#define APBPeriph_TRACE_CLOCK (BIT_SOC_ACTCK_TRACE_EN)
|
|
|
|
/* 0x210 REG_SOC_FUNC_EN */
|
|
#define APBPeriph_SECURITY_ENGINE BIT_SOC_SECURITY_ENGINE_EN
|
|
#define APBPeriph_GTIMER BIT_SOC_GTIMER_EN
|
|
#define APBPeriph_GDMA1 BIT_SOC_GDMA1_EN
|
|
#define APBPeriph_GDMA0 BIT_SOC_GDMA0_EN
|
|
#define APBPeriph_FLASH BIT_SOC_FLASH_EN
|
|
#define APBPeriph_LXBUS BIT_SOC_LXBUS_EN
|
|
|
|
/* rtl8711b_wifi.h (it doesn't actually exist) :) */
|
|
|
|
/* 8192C Cmd9346CR bits (Offset 0xA, 16bit) */
|
|
#define CmdEEPROM_En (1 << 5) // EEPROM enable when set 1
|
|
/* System EEPROM select, 0: boot from E-FUSE, 1: The EEPROM used is 9346 */
|
|
#define CmdEERPOMSEL (1 << 4)
|
|
#define Cmd9346CR_9356SEL (1 << 4)
|
|
|
|
/* 8192C GPIO MUX Configuration Register (offset 0x40, 4 byte) */
|
|
#define GPIOSEL_GPIO (1 << 0)
|
|
#define GPIOSEL_ENBT (1 << 5)
|
|
|
|
/* 8192C GPIO PIN Control Register (offset 0x44, 4 byte) */
|
|
/* TODO: we don't have REG_GPIO_PIN_CTRL_8711? :^) */
|
|
#define GPIO_VAL_IN REG_GPIO_PIN_CTRL_8711 // GPIO pins input value
|
|
#define GPIO_VAL_OUT (REG_GPIO_PIN_CTRL_8711 + 1) // GPIO pins output value
|
|
/* GPIO pins output enable when a bit is set to "1"; otherwise, input is
|
|
* configured. */
|
|
#define GPIO_IO_SEL (REG_GPIO_PIN_CTRL_8711 + 2)
|
|
#define GPIO_MOD (REG_GPIO_PIN_CTRL_8711 + 3)
|
|
#define HAL_8192C_HW_GPIO_WPS_BIT (1 << 2)
|
|
|
|
/* 8723/8188E Host System Interrupt Mask Register (offset 0x58, 32 byte) */
|
|
#define HSIMR_GPIO12_0_INT_EN (1 << 0)
|
|
#define HSIMR_SPS_OCP_INT_EN (1 << 5)
|
|
#define HSIMR_RON_INT_EN (1 << 6)
|
|
#define HSIMR_PDN_INT_EN (1 << 7)
|
|
#define HSIMR_GPIO9_INT_EN (1 << 25)
|
|
|
|
/* 8723/8188E Host System Interrupt Status Register (offset 0x5C, 32 byte) */
|
|
#define HSISR_GPIO12_0_INT (1 << 0)
|
|
#define HSISR_SPS_OCP_INT (1 << 5)
|
|
#define HSISR_RON_INT_EN (1 << 6)
|
|
#define HSISR_PDNINT (1 << 7)
|
|
#define HSISR_GPIO9_INT (1 << 25)
|
|
|
|
/* 8192C (MSR) Media Status Register (Offset 0x4C, 8 bits) */
|
|
/*
|
|
Network Type
|
|
00: No link
|
|
01: Link in ad hoc network
|
|
10: Link in infrastructure network
|
|
11: AP mode
|
|
Default: 00b.
|
|
*/
|
|
#define MSR_NOLINK 0x00
|
|
#define MSR_ADHOC 0x01
|
|
#define MSR_INFRA 0x02
|
|
#define MSR_AP 0x03
|
|
|
|
/* 88EU (MSR) Media Status Register (Offset 0x4C, 8 bits) */
|
|
#define USB_INTR_CONTENT_HISR_OFFSET 48
|
|
#define USB_INTR_CONTENT_HISRE_OFFSET 52
|
|
|
|
/* 6. Adaptive Control Registers (Offset: 0x0160 - 0x01CF) */
|
|
/* 8192C Response Rate Set Register (offset 0x181, 24bits) */
|
|
#define RRSR_1M (1 << 0)
|
|
#define RRSR_2M (1 << 1)
|
|
#define RRSR_5_5M (1 << 2)
|
|
#define RRSR_11M (1 << 3)
|
|
#define RRSR_6M (1 << 4)
|
|
#define RRSR_9M (1 << 5)
|
|
#define RRSR_12M (1 << 6)
|
|
#define RRSR_18M (1 << 7)
|
|
#define RRSR_24M (1 << 8)
|
|
#define RRSR_36M (1 << 9)
|
|
#define RRSR_48M (1 << 10)
|
|
#define RRSR_54M (1 << 11)
|
|
#define RRSR_MCS0 (1 << 12)
|
|
#define RRSR_MCS1 (1 << 13)
|
|
#define RRSR_MCS2 (1 << 14)
|
|
#define RRSR_MCS3 (1 << 15)
|
|
#define RRSR_MCS4 (1 << 16)
|
|
#define RRSR_MCS5 (1 << 17)
|
|
#define RRSR_MCS6 (1 << 18)
|
|
#define RRSR_MCS7 (1 << 19)
|
|
|
|
/* 8192C Response Rate Set Register (offset 0x1BF, 8bits) */
|
|
/* WOL bit information */
|
|
#define HAL92C_WOL_PTK_UPDATE_EVENT (1 << 0)
|
|
#define HAL92C_WOL_GTK_UPDATE_EVENT (1 << 1)
|
|
|
|
/* 8192C Rate Definition */
|
|
/* CCK */
|
|
#define RATR_1M 0x00000001
|
|
#define RATR_2M 0x00000002
|
|
#define RATR_55M 0x00000004
|
|
#define RATR_11M 0x00000008
|
|
/* OFDM */
|
|
#define RATR_6M 0x00000010
|
|
#define RATR_9M 0x00000020
|
|
#define RATR_12M 0x00000040
|
|
#define RATR_18M 0x00000080
|
|
#define RATR_24M 0x00000100
|
|
#define RATR_36M 0x00000200
|
|
#define RATR_48M 0x00000400
|
|
#define RATR_54M 0x00000800
|
|
/* MCS 1 Spatial Stream */
|
|
#define RATR_MCS0 0x00001000
|
|
#define RATR_MCS1 0x00002000
|
|
#define RATR_MCS2 0x00004000
|
|
#define RATR_MCS3 0x00008000
|
|
#define RATR_MCS4 0x00010000
|
|
#define RATR_MCS5 0x00020000
|
|
#define RATR_MCS6 0x00040000
|
|
#define RATR_MCS7 0x00080000
|
|
/* MCS 2 Spatial Stream */
|
|
#define RATR_MCS8 0x00100000
|
|
#define RATR_MCS9 0x00200000
|
|
#define RATR_MCS10 0x00400000
|
|
#define RATR_MCS11 0x00800000
|
|
#define RATR_MCS12 0x01000000
|
|
#define RATR_MCS13 0x02000000
|
|
#define RATR_MCS14 0x04000000
|
|
#define RATR_MCS15 0x08000000
|
|
|
|
/* NOTE: For 92CU - Ziv */
|
|
/* CCK */
|
|
#define RATE_1M (1 << 0)
|
|
#define RATE_2M (1 << 1)
|
|
#define RATE_5_5M (1 << 2)
|
|
#define RATE_11M (1 << 3)
|
|
/* OFDM */
|
|
#define RATE_6M (1 << 4)
|
|
#define RATE_9M (1 << 5)
|
|
#define RATE_12M (1 << 6)
|
|
#define RATE_18M (1 << 7)
|
|
#define RATE_24M (1 << 8)
|
|
#define RATE_36M (1 << 9)
|
|
#define RATE_48M (1 << 10)
|
|
#define RATE_54M (1 << 11)
|
|
/* MCS 1 Spatial Stream */
|
|
#define RATE_MCS0 (1 << 12)
|
|
#define RATE_MCS1 (1 << 13)
|
|
#define RATE_MCS2 (1 << 14)
|
|
#define RATE_MCS3 (1 << 15)
|
|
#define RATE_MCS4 (1 << 16)
|
|
#define RATE_MCS5 (1 << 17)
|
|
#define RATE_MCS6 (1 << 18)
|
|
#define RATE_MCS7 (1 << 19)
|
|
/* MCS 2 Spatial Stream */
|
|
#define RATE_MCS8 (1 << 20)
|
|
#define RATE_MCS9 (1 << 21)
|
|
#define RATE_MCS10 (1 << 22)
|
|
#define RATE_MCS11 (1 << 23)
|
|
#define RATE_MCS12 (1 << 24)
|
|
#define RATE_MCS13 (1 << 25)
|
|
#define RATE_MCS14 (1 << 26)
|
|
#define RATE_MCS15 (1 << 27)
|
|
|
|
/* ALL CCK Rate */
|
|
#define RATE_ALL_CCK RATR_1M | RATR_2M | RATR_55M | RATR_11M
|
|
#define RATE_ALL_OFDM_AG \
|
|
RATR_6M | RATR_9M | RATR_12M | RATR_18M | RATR_24M | RATR_36M | RATR_48M | \
|
|
RATR_54M
|
|
#define RATE_ALL_OFDM_1SS \
|
|
RATR_MCS0 | RATR_MCS1 | RATR_MCS2 | RATR_MCS3 | RATR_MCS4 | RATR_MCS5 | \
|
|
RATR_MCS6 | RATR_MCS7
|
|
#define RATE_ALL_OFDM_2SS \
|
|
RATR_MCS8 | RATR_MCS9 | RATR_MCS10 | RATR_MCS11 | RATR_MCS12 | RATR_MCS13 | \
|
|
RATR_MCS14 | RATR_MCS15
|
|
|
|
#define RATE_BITMAP_ALL 0xFFFFF
|
|
|
|
/* Only use CCK 1M rate for ACK */
|
|
#define RATE_RRSR_CCK_ONLY_1M 0xFFFF1
|
|
|
|
/* 8192C BW_OPMODE bits (Offset 0x203, 8bit) */
|
|
#define BW_OPMODE_20MHZ (1 << 2)
|
|
#define BW_OPMODE_5G (1 << 1)
|
|
|
|
/* 10. Power Save Control Registers (Offset: 0x0260 - 0x02DF) */
|
|
#define WOW_PMEN (1 << 0) // Power management Enable.
|
|
#define WOW_WOMEN (1 << 1) // WoW function on or off.
|
|
#define WOW_MAGIC (1 << 2) // Magic packet
|
|
#define WOW_UWF (1 << 3) // Unicast Wakeup frame.
|
|
|
|
/* 8711 IMR/ISR bits (offset 0x80, 8bits) */
|
|
#if 0
|
|
// The interrupt mask from WL page 1 interrupt source
|
|
#define IMR_WL_FTINT_MSK_8711B (1 << 31)
|
|
// P2P NoA RF off time indication interrupt mask
|
|
#define IMR_P2P_RFOFF_INT_MSK_8711B (1 << 9)
|
|
// P2P NoA RF on time indication interrupt mask
|
|
#define IMR_P2P_RFON_INT_MSK_8711B (1 << 8)
|
|
#define IMR_PSTIMER_MSK_8711B (1 << 6) // Enable PSTimer interrupt source
|
|
#define IMR_TIMEOUT1_MSK_8711B (1 << 5) // Enable Timer1 interrupt source
|
|
#define IMR_TIMEOUT0_MSK_8711B (1 << 4) // Enable Timer0 interrupt source
|
|
// Enable MTI_BCNIVLEAR _INT
|
|
// This interrupt is issued at the time set by DRVERLYINT register before TBTT time.
|
|
#define IMR_MTI_BCNIVLEAR_INT_MSK_8711B (1 << 1)
|
|
#define IMR_BCNERLY_MSK_8711B (1 << 0)
|
|
#endif
|
|
|
|
#define IMR_MSK_CPWM2 (1 << 25)
|
|
#define IMR_MSK_CPWM (1 << 24)
|
|
/* "Rx packet buffer OverflowSet this bit to one when Rx packet buffer write
|
|
* pointer hits read pointer." */
|
|
#define IMR_FOVW_MSK_8711B (1 << 23)
|
|
#define IMR_TXBCN0ERR_8711B (1 << 20) // Transmit Beacon0 Error
|
|
#define IMR_TXBCN0OK_8711B (1 << 19) // Transmit Beacon0 OK
|
|
|
|
/* "Transmit packet buffer Overflow.This bit is set to 1 when one or more of the
|
|
* hardware transmit queues is full" */
|
|
#define IMR_TXFOVW_MSK_8711B (1 << 18)
|
|
|
|
/* Enable TSF_BIT32_TOGGLE interrupt source */
|
|
#define IMR_TSF_BIT32_TOGGLE_MSK_V1_8711B (1 << 17)
|
|
|
|
/* This bit masks the CTWindow End interrupt. */
|
|
#define IMR_CTWEndINT_MSK_8711B (1 << 13)
|
|
|
|
/* BCNDMA interrupt masks for 8711B
|
|
* When BCNDMA interval arrives before TBTTx, these interrupts
|
|
* inform MCU to prepare related beacon tasks.
|
|
*/
|
|
#define IMR_BCNDMA9_MSK_8711B (1 << 9)
|
|
#define IMR_BCNDMA8_MSK_8711B (1 << 8)
|
|
#define IMR_BCNDMA7_MSK_8711B (1 << 7)
|
|
#define IMR_BCNDMA6_MSK_8711B (1 << 6)
|
|
#define IMR_BCNDMA5_MSK_8711B (1 << 5)
|
|
#define IMR_BCNDMA4_MSK_8711B (1 << 4)
|
|
#define IMR_BCNDMA3_MSK_8711B (1 << 3)
|
|
#define IMR_BCNDMA2_MSK_8711B (1 << 2)
|
|
#define IMR_BCNDMA1_MSK_8711B (1 << 1)
|
|
#define IMR_BCNDMA0_MSK_8711B (1 << 0)
|
|
|
|
#if 0
|
|
/* 8711 IMR/ISR bits (offset 0x134, 8bits) */
|
|
/* Be a beamformer, this interrupt is issued at the time after sounding finish */
|
|
#define IMR_SOUND_DONE_MSK_8711B (1 << 30)
|
|
/* When TRY_FINISH is deasserted, this interrupt is issued to inform MCU */
|
|
#define IMR_TRY_DONE_MSK_8711B (1 << 29)
|
|
#define IMR_TXRPT_CNT_FULL_MSK_8711B (1 << 28)
|
|
#define IMR_WLACTOFF_INT_EN_8711B (1 << 27)
|
|
#define IMR_WLACTON_INT_EN_8711B (1 << 26)
|
|
#define IMR_TXPKTIN_INT_EN_8711B (1 << 25)
|
|
#define IMR_RX_UMD0_EN_8711B (1 << 22)
|
|
#define IMR_RX_UMD1_EN_8711B (1 << 21)
|
|
#define IMR_RX_BMD0_EN_8711B (1 << 20)
|
|
#define IMR_RX_BMD1_EN_8711B (1 << 19)
|
|
#define IMR_BCN_RX_INT_EN_8711B (1 << 18)
|
|
#define IMR_TBTTINT_MSK_8711B (1 << 17)
|
|
|
|
#define IMR_STBY_MSK_8711B (1 << 7) // Lower Power Standby Interrupt mask
|
|
#define IMR_RXDONE_MSK_8711B (1 << 3) // Rx Packet done for 8051
|
|
/* FWHW/ TXDMA/ RXDMA/ WMAC error status interrupt */
|
|
#define IMR_ERRORHDL_MSK_8711B (1 << 2)
|
|
/* CCX PKT TX Report Interrupt */
|
|
#define IMR_TXCCX_MSK_FW_8711B (1 << 1)
|
|
/* TX Finish (Ack/BA process Finish) Interrupt. */
|
|
#define IMR_TXCLOSE_MSK_8711B (1 << 0)
|
|
|
|
#endif
|
|
|
|
/* 8711 IMR/ISR bits (offset 0x13C, 8bits) */
|
|
#define IMR_TXBCN1ERR_8711B (1 << 15) // Transmit Beacon1 Error
|
|
#define IMR_TXBCN1OK_8711B (1 << 14) // Transmit Beacon1 OK
|
|
|
|
/* 8711 IMR/ISR bits offset 0x3EC, 8bits) */
|
|
#define IMR_BCNDERR7_8711B (1 << 31) // Beacon Queue DMA Error
|
|
#define IMR_BCNDERR6_8711B (1 << 30) // Beacon Queue DMA Error
|
|
#define IMR_BCNDERR5_8711B (1 << 29) // Beacon Queue DMA Error
|
|
#define IMR_BCNDERR4_8711B (1 << 28) // Beacon Queue DMA Error
|
|
#define IMR_BCNDERR3_8711B (1 << 27) // Beacon Queue DMA Error
|
|
#define IMR_BCNDERR2_8711B (1 << 26) // Beacon Queue DMA Error
|
|
#define IMR_BCNDERR1_8711B (1 << 25) // Beacon Queue DMA Error
|
|
#define IMR_BCNDERR0_8711B (1 << 24) // Beacon Queue DMA Error
|
|
#define IMR_BCNDMAOK7_8711B (1 << 23) // Beacon DMA OK Interrupt 7
|
|
#define IMR_BCNDMAOK6_8711B (1 << 22) // Beacon DMA OK Interrupt 6
|
|
#define IMR_BCNDMAOK5_8711B (1 << 21) // Beacon DMA OK Interrupt 5
|
|
#define IMR_BCNDMAOK4_8711B (1 << 20) // Beacon DMA OK Interrupt 4
|
|
#define IMR_BCNDMAOK3_8711B (1 << 19) // Beacon DMA OK Interrupt 3
|
|
#define IMR_BCNDMAOK2_8711B (1 << 18) // Beacon DMA OK Interrupt 2
|
|
#define IMR_BCNDMAOK1_8711B (1 << 17) // Beacon DMA OK Interrupt 1
|
|
#define IMR_BCNDMAOK0_8711B (1 << 16) // Beacon DMA OK Interrupt 0
|
|
#define IMR_H7DOK_8711B (1 << 15) // High Queue DMA OK Interrup 7
|
|
#define IMR_H6DOK_8711B (1 << 14) // High Queue DMA OK Interrup 6
|
|
#define IMR_H5DOK_8711B (1 << 13) // High Queue DMA OK Interrup 5
|
|
#define IMR_H4DOK_8711B (1 << 12) // High Queue DMA OK Interrup 4
|
|
#define IMR_H3DOK_8711B (1 << 11) // High Queue DMA OK Interrup 3
|
|
#define IMR_H2DOK_8711B (1 << 10) // High Queue DMA OK Interrup 2
|
|
#define IMR_H1DOK_8711B (1 << 9) // High Queue DMA OK Interrup 1
|
|
#define IMR_H0DOK_8711B (1 << 8) // High Queue DMA OK Interrup 1
|
|
#define IMR_MGNTDOK_8711B (1 << 6) // Management Queue DMA OK
|
|
#define IMR_BKDOK_8711B (1 << 5) // AC_BK DMA OK
|
|
#define IMR_BEDOK_8711B (1 << 4) // AC_BE DMA OK
|
|
#define IMR_VIDOK_8711B (1 << 3) // AC_VI DMA OK
|
|
#define IMR_VODOK_8711B (1 << 2) // AC_VO DMA OK
|
|
#define IMR_RDU_8711B (1 << 1) // Rx Descriptor Unavailable
|
|
#define IMR_ROK_8711B (1 << 0) // Receive DMA OK
|
|
|
|
/*===================================================================
|
|
=====================================================================
|
|
Here the register defines are for 92C. When the define is as same with 92C,
|
|
we will use the 92C's define for the consistency
|
|
So the following defines for 92C is not entire!!!!!!
|
|
=====================================================================
|
|
=====================================================================*/
|
|
/*
|
|
* Based on Datasheet V33---090401
|
|
* Register Summary
|
|
* Current IOREG MAP
|
|
* 0x0000h ~ 0x00FFh System Configuration (256 Bytes)
|
|
* 0x0100h ~ 0x01FFh MACTOP General Configuration (256 Bytes)
|
|
* 0x0200h ~ 0x027Fh TXDMA Configuration (128 Bytes)
|
|
* 0x0280h ~ 0x02FFh RXDMA Configuration (128 Bytes)
|
|
* 0x0300h ~ 0x03FFh PCIE EMAC Reserved Region (256 Bytes)
|
|
* 0x0400h ~ 0x04FFh Protocol Configuration (256 Bytes)
|
|
* 0x0500h ~ 0x05FFh EDCA Configuration (256 Bytes)
|
|
* 0x0600h ~ 0x07FFh WMAC Configuration (512 Bytes)
|
|
* 0x2000h ~ 0x3FFFh 8051 FW Download Region (8196 Bytes)
|
|
*/
|
|
|
|
/* 8711 (TXPAUSE) transmission pause (Offset 0x522, 8 bits) */
|
|
#define StopBecon (1 << 6)
|
|
#define StopHigh (1 << 5)
|
|
#define StopMgt (1 << 4)
|
|
#define StopVO (1 << 3)
|
|
#define StopVI (1 << 2)
|
|
#define StopBE (1 << 1)
|
|
#define StopBK (1 << 0)
|
|
|
|
/* 8192C Regsiter Bit and Content definition */
|
|
/* 0x0000h ~ 0x00FFh System Configuration */
|
|
/* 2 SYS_ISO_CTRL */
|
|
#define ISO_MD2PP (1 << 0)
|
|
#define ISO_UA2USB (1 << 1)
|
|
#define ISO_UD2CORE (1 << 2)
|
|
#define ISO_PA2PCIE (1 << 3)
|
|
#define ISO_PD2CORE (1 << 4)
|
|
#define ISO_IP2MAC (1 << 5)
|
|
#define ISO_DIOP (1 << 6)
|
|
#define ISO_DIOE (1 << 7)
|
|
#define ISO_EB2CORE (1 << 8)
|
|
#define ISO_DIOR (1 << 9)
|
|
#define PWC_EV12V (1 << 15)
|
|
|
|
/* 2 SYS_FUNC_EN */
|
|
#define FEN_BBRSTB (1 << 0)
|
|
#define FEN_BB_GLB_RSTn (1 << 1)
|
|
#define FEN_USBA (1 << 2)
|
|
#define FEN_UPLL (1 << 3)
|
|
#define FEN_USBD (1 << 4)
|
|
#define FEN_DIO_PCIE (1 << 5)
|
|
#define FEN_PCIEA (1 << 6)
|
|
#define FEN_PPLL (1 << 7)
|
|
#define FEN_PCIED (1 << 8)
|
|
#define FEN_DIOE (1 << 9)
|
|
#define FEN_CPUEN (1 << 10)
|
|
#define FEN_DCORE (1 << 11)
|
|
#define FEN_ELDR (1 << 12)
|
|
#define FEN_DIO_RF (1 << 13)
|
|
#define FEN_HWPDN (1 << 14)
|
|
#define FEN_MREGEN (1 << 15)
|
|
|
|
/* 2 APS_FSMCO */
|
|
#define PFM_LDALL (1 << 0)
|
|
#define PFM_ALDN (1 << 1)
|
|
#define PFM_LDKP (1 << 2)
|
|
#define PFM_WOWL (1 << 3)
|
|
#define EnPDN (1 << 4)
|
|
#define PDN_PL (1 << 5)
|
|
#define APFM_ONMAC (1 << 8)
|
|
#define APFM_OFF (1 << 9)
|
|
#define APFM_RSM (1 << 10)
|
|
#define AFSM_HSUS (1 << 11)
|
|
#define AFSM_PCIE (1 << 12)
|
|
#define APDM_MAC (1 << 13)
|
|
#define APDM_HOST (1 << 14)
|
|
#define APDM_HPDN (1 << 15)
|
|
#define RDY_MACON (1 << 16)
|
|
#define SUS_HOST (1 << 17)
|
|
#define ROP_ALD (1 << 20)
|
|
#define ROP_PWR (1 << 21)
|
|
#define ROP_SPS (1 << 22)
|
|
#define SOP_MRST (1 << 25)
|
|
#define SOP_FUSE (1 << 26)
|
|
#define SOP_ABG (1 << 27)
|
|
#define SOP_AMB (1 << 28)
|
|
#define SOP_RCK (1 << 29)
|
|
#define SOP_A8M (1 << 30)
|
|
#define XOP_BTCK (1 << 31)
|
|
|
|
/* 2 SYS_CLKR */
|
|
#define ANAD16V_EN (1 << 0)
|
|
#define ANA8M (1 << 1)
|
|
#define MACSLP (1 << 4)
|
|
#define LOADER_CLK_EN (1 << 5)
|
|
|
|
/* 2 9346CR */
|
|
|
|
#define BOOT_FROM_EEPROM (1 << 4)
|
|
#define EEPROM_EN (1 << 5)
|
|
|
|
/* 2 RF_CTRL */
|
|
#define RF_EN (1 << 0)
|
|
#define RF_RSTB (1 << 1)
|
|
#define RF_SDMRSTB (1 << 2)
|
|
|
|
/* 2 LDOV12D_CTRL */
|
|
#define LDV12_EN (1 << 0)
|
|
#define LDV12_SDBY (1 << 1)
|
|
#define LPLDO_HSM (1 << 2)
|
|
#define LPLDO_LSM_DIS (1 << 3)
|
|
#define _LDV12_VADJ(x) (((x) & 0xF) << 4)
|
|
|
|
/* 2 EFUSE_TEST (For RTL8723 partially) */
|
|
#define EF_TRPT (1 << 7)
|
|
/* 00: Wifi Efuse, 01: BT Efuse0, 10: BT Efuse1, 11: BT Efuse2 */
|
|
#define EF_CELL_SEL ((1 << 8) | (1 << 9))
|
|
#define LDOE25_EN (1 << 31)
|
|
#define EFUSE_SEL(x) (((x) & 0x3) << 8)
|
|
#define EFUSE_SEL_MASK 0x300
|
|
#define EFUSE_WIFI_SEL_0 0x0
|
|
#define EFUSE_BT_SEL_0 0x1
|
|
#define EFUSE_BT_SEL_1 0x2
|
|
#define EFUSE_BT_SEL_2 0x3
|
|
|
|
/* 2 8051FWDL */
|
|
/* 2 MCUFWDL */
|
|
#define MCUFWDL_EN (1 << 0)
|
|
#define MCUFWDL_RDY (1 << 1)
|
|
#define FWDL_ChkSum_rpt (1 << 2)
|
|
#define MACINI_RDY (1 << 3)
|
|
#define BBINI_RDY (1 << 4)
|
|
#define RFINI_RDY (1 << 5)
|
|
#define WINTINI_RDY (1 << 6)
|
|
#define RAM_DL_SEL (1 << 7)
|
|
#define ROM_DLEN (1 << 19)
|
|
#define CPRST (1 << 23)
|
|
|
|
/* 2 REG_SYS_CFG */
|
|
#define XCLK_VLD (1 << 0)
|
|
#define ACLK_VLD (1 << 1)
|
|
#define UCLK_VLD (1 << 2)
|
|
#define PCLK_VLD (1 << 3)
|
|
#define PCIRSTB (1 << 4)
|
|
#define V15_VLD (1 << 5)
|
|
#define TRP_B15V_EN (1 << 7)
|
|
#define SIC_IDLE (1 << 8)
|
|
#define BD_MAC2 (1 << 9)
|
|
#define BD_MAC1 (1 << 10)
|
|
#define IC_MACPHY_MODE (1 << 11)
|
|
#define CHIP_VER ((1 << 12) | (1 << 13) | (1 << 14) | (1 << 15))
|
|
#define BT_FUNC (1 << 16)
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#define VENDOR_ID (1 << 19)
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#define PAD_HWPD_IDN (1 << 22)
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#define TRP_VAUX_EN (1 << 23) /* RTL ID */
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#define TRP_BT_EN (1 << 24)
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#define BD_PKG_SEL (1 << 25)
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#define BD_HCI_SEL (1 << 26)
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#define TYPE_ID (1 << 27)
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#define CHIP_VER_RTL_MASK 0xF000 /* Bit 12 ~ 15 */
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#define CHIP_VER_RTL_SHIFT 12
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/* 0x0100h ~ 0x01FFh MACTOP General Configuration */
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/* 2 Function Enable Registers */
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/* 2 CR 0x0100-0x0103 */
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#define HCI_TXDMA_EN (1 << 0)
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#define HCI_RXDMA_EN (1 << 1)
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#define TXDMA_EN (1 << 2)
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#define RXDMA_EN (1 << 3)
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#define PROTOCOL_EN (1 << 4)
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#define SCHEDULE_EN (1 << 5)
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#define MACTXEN (1 << 6)
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#define MACRXEN (1 << 7)
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#define ENSWBCN (1 << 8)
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#define ENSEC (1 << 9)
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#define CALTMR_EN (1 << 10) /* 32k CAL TMR enable */
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/* Network type */
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#define _NETTYPE(x) (((x) & 0x3) << 16)
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#define MASK_NETTYPE 0x30000
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#define NT_NO_LINK 0x0
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#define NT_LINK_AD_HOC 0x1
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#define NT_LINK_AP 0x2
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#define NT_AS_AP 0x3
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/* 2 PBP - Page Size Register 0x0104 */
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#define GET_RX_PAGE_SIZE(value) ((value) & 0xF)
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#define GET_TX_PAGE_SIZE(value) (((value) & 0xF0) >> 4)
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#define _PSRX_MASK 0xF
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#define _PSTX_MASK 0xF0
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#define _PSRX(x) (x)
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#define _PSTX(x) ((x) << 4)
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#define PBP_64 0x0
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#define PBP_128 0x1
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#define PBP_256 0x2
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#define PBP_512 0x3
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#define PBP_1024 0x4
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/* 2 TX/RXDMA 0x010C */
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#define RXDMA_ARBBW_EN (1 << 0)
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#define RXSHFT_EN (1 << 1)
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#define RXDMA_AGG_EN (1 << 2)
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#define QS_VO_QUEUE (1 << 8)
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#define QS_VI_QUEUE (1 << 9)
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#define QS_BE_QUEUE (1 << 10)
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#define QS_BK_QUEUE (1 << 11)
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#define QS_MANAGER_QUEUE (1 << 12)
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#define QS_HIGH_QUEUE (1 << 13)
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#define HQSEL_VOQ (1 << 0)
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#define HQSEL_VIQ (1 << 1)
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#define HQSEL_BEQ (1 << 2)
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#define HQSEL_BKQ (1 << 3)
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#define HQSEL_MGTQ (1 << 4)
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#define HQSEL_HIQ (1 << 5)
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/* For normal driver, 0x10C */
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#define _TXDMA_HIQ_MAP(x) (((x) & 0x3) << 14)
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#define _TXDMA_MGQ_MAP(x) (((x) & 0x3) << 12)
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#define _TXDMA_BKQ_MAP(x) (((x) & 0x3) << 10)
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#define _TXDMA_BEQ_MAP(x) (((x) & 0x3) << 8)
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#define _TXDMA_VIQ_MAP(x) (((x) & 0x3) << 6)
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#define _TXDMA_VOQ_MAP(x) (((x) & 0x3) << 4)
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#define QUEUE_LOW 1
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#define QUEUE_NORMAL 2
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#define QUEUE_HIGH 3
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/* 2 REG_C2HEVT_CLEAR 0x01AF */
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/* Set by driver and notify FW that the driver has read the C2H command message
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*/
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#define C2H_EVT_HOST_CLOSE 0x00
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/* Set by FW indicating that FW had set the C2H command message and it's not yet
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* read by driver. */
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#define C2H_EVT_FW_CLOSE 0xFF
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/* 2 LLT_INIT 0x01E0 */
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#define _LLT_NO_ACTIVE 0x0
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#define _LLT_WRITE_ACCESS 0x1
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#define _LLT_READ_ACCESS 0x2
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#define _LLT_INIT_DATA(x) ((x) & 0xFF)
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#define _LLT_INIT_ADDR(x) (((x) & 0xFF) << 8)
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#define _LLT_OP(x) (((x) & 0x3) << 30)
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#define _LLT_OP_VALUE(x) (((x) >> 30) & 0x3)
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/* 0x0200h ~ 0x027Fh TXDMA Configuration */
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/* 2 TDECTL 0x0208 */
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#define BLK_DESC_NUM_SHIFT 4
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#define BLK_DESC_NUM_MASK 0xF
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/* 2 TXDMA_OFFSET_CHK 0x020C */
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#define DROP_DATA_EN (1 << 9)
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/* 0x0280h ~ 0x028Bh RX DMA Configuration */
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/* REG_RXDMA_CONTROL, 0x0286h */
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/**
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* 2 REG_RXPKT_NUM, 0x0284
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* Write only. When this bit is set, RXDMA will decrease RX PKT counter by one.
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* Before this bit is polled, FW shall update RXFF_RD_PTR first. This register
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* is write pulse and auto clear.
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*/
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#define RXPKT_RELEASE_POLL (1 << 0)
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/**
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* Read only. When RXMA finishes on-going DMA operation, RXMDA will report idle
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* state in this bit. FW can start releasing packets after RXDMA entering idle
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* mode.
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*/
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#define RXDMA_IDLE (1 << 1)
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/**
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*
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* When this bit is set, RXDMA will enter this mode after on-going RXDMA packet
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* to host completed, and stop DMA packet to host. RXDMA will then report
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* Default: 0;
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*/
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#define RW_RELEASE_EN (1 << 2)
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/* 0x0300h ~ 0x03FFh LxBUS Registers */
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/* some bit settings */
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#define LXBUS_CTRL_BIT8 (1 << 8) /* Control register bit 8 */
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#define LXBUS_K32_CTRL_BIT0 (1 << 0) /* 32K Control bit 0 */
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#define LXBUS_K32_CTRL_BIT6 (1 << 6) /* 32K Control bit 6 */
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#define LXBUS_K32_CTRL_BIT7 (1 << 7) /* 32K Control bit 7 */
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/* DMA config */
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#define LXBUS_DMA_CFG_TYPE1 0x1004 /* DMA config type 1 */
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#define LXBUS_DMA_CFG_TYPE2 0x2004 /* DMA config type 2 */
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#define LXBUS_DMA_CFG_TYPE3 0x1002 /* DMA config type 3 */
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/* 0x0400h ~ 0x047Fh Protocol Configuration */
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/* 2 FWHW_TXQ_CTRL 0x0420 */
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#define EN_AMPDU_RTY_NEW (1 << 7)
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/* 2 REG_LIFECTRL_CTRL 0x0426 */
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#define HAL92C_EN_PKT_LIFE_TIME_BK (1 << 3)
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#define HAL92C_EN_PKT_LIFE_TIME_BE (1 << 2)
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#define HAL92C_EN_PKT_LIFE_TIME_VI (1 << 1)
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#define HAL92C_EN_PKT_LIFE_TIME_VO (1 << 0)
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#define HAL92C_MSDU_LIFE_TIME_UNIT 128 // in us, said by Tim.
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/* 2 SPEC SIFS 0x0428 */
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#define _SPEC_SIFS_CCK(x) ((x) & 0xFF)
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#define _SPEC_SIFS_OFDM(x) (((x) & 0xFF) << 8)
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/* 2 RL 0x042A */
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#define RETRY_LIMIT_SHORT_SHIFT 8
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#define RETRY_LIMIT_LONG_SHIFT 0
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#define _LRL(x) ((x) & 0x3F)
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#define _SRL(x) (((x) & 0x3F) << 8)
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/* 0x0500h ~ 0x05FFh EDCA Configuration */
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/* 2 EDCA setting 0x050C */
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#define AC_PARAM_TXOP_LIMIT_OFFSET 16
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#define AC_PARAM_ECW_MAX_OFFSET 12
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#define AC_PARAM_ECW_MIN_OFFSET 8
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#define AC_PARAM_AIFS_OFFSET 0
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/* 2 BCN_CTRL 0x0550 */
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#define EN_TXBCN_RPT (1 << 2)
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#define EN_BCN_FUNCTION (1 << 3)
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/* 2 TxPause 0x0522 */
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#define STOP_BCNQ (1 << 6)
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/* 2 ACMHWCTRL 0x05C0 */
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#define AcmHw_HwEn_8723B (1 << 0)
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#define AcmHw_VoqEn_8723B (1 << 1)
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#define AcmHw_ViqEn_8723B (1 << 2)
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#define AcmHw_BeqEn_8723B (1 << 3)
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#define AcmHw_VoqStatus_8723B (1 << 5)
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#define AcmHw_ViqStatus_8723B (1 << 6)
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#define AcmHw_BeqStatus_8723B (1 << 7)
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/* 0x0600h ~ 0x07FFh WMAC Configuration */
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/* 2 TCR 0x0604 */
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#define DIS_GCLK (1 << 1)
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#define PAD_SEL (1 << 2)
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#define PWR_ST (1 << 6)
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#define PWRBIT_OW_EN (1 << 7)
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#define ACRC (1 << 8)
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#define CFENDFORM (1 << 9)
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#define ICV (1 << 10)
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/* 8711 (RCR) Receive Configuration Register (Offset 0x608, 32 bits) */
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/* WMAC append FCS after payload */
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#define RCR_APPFCS (1 << 31)
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/* MACRX will retain the MIC at the bottom of the packet */
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#define RCR_APP_MIC (1 << 30) //
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/* MACRX will retain the ICV at the bottom of the packet. */
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#define RCR_APP_ICV (1 << 29)
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/* HY Status is appended before RX packet in RXFF */
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#define RCR_APP_PHYST_RXFF (1 << 28)
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/* SSN of previous TXBA is appended as after original RXDESC as the 4th DW of
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* RXDESC */
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#define RCR_APP_BA_SSN (1 << 27)
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#define RCR_RSVD_BIT26 (1 << 26) // Reserved
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#define RCR_TCPOFLD_EN (1 << 25) // Enable TCP checksum offload
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/* Enable Multiple BssId. Only response ACK to the packets whose DID(A1)
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* matching to the addresses in the MBSSID CAM Entries. */
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#define RCR_ENMBID (1 << 24)
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/* Enable LSIG TXOP Protection function. Search KEYCAM for each rx packet to
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* check if LSIGEN bit is set. */
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#define RCR_LSIGEN (1 << 23)
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/* Enable immediate MCS Feedback function. When Rx packet with MRQ = 1'b1, then
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* search KEYCAM to find sender's MCS Feedback function and send response. */
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#define RCR_MFBEN (1 << 22)
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/* WMAC clock stop and reset after BB transmitting end; 0: enable, 1: disable */
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#define RCR_MAC_RESET (1 << 19)
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#define RCR_TIM_PARSER_EN (1 << 18) // RX Beacon TIM Parser.
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#define RCR_BM_DATA_EN (1 << 17) // Broadcast data packet interrupt enable.
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#define RCR_UC_DATA_EN (1 << 16) // Unicast data packet interrupt enable.
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#define RCR_HTC_LOC_CTRL (1 << 14) // MFC<--HTC=1 MFC-->HTC=0
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/* Accept management type frame */
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#define RCR_AMF (1 << 13)
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/* // Accept control type frame. Control frames BA, BAR, and PS-Poll
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|
* (when in AP mode) are not controlled by this bit. They are controlled by ADF.
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*/
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#define RCR_ACF (1 << 12)
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/* Accept data type frame. This bit also regulates BA, BAR, and PS-Poll (AP mode
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* only). */
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#define RCR_ADF (1 << 11)
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/* Accept ICV error packet */
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#define RCR_AICV (1 << 9)
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/* Accept CRC32 error packet */
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#define RCR_ACRC32 (1 << 8)
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/* Accept BSSID match packet (Rx beacon, probe rsp) */
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|
#define RCR_CBSSID_BCN (1 << 7)
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|
#define RCR_CBSSID_DATA (1 << 6) // Accept BSSID match packet (Data)
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#define RCR_CBSSID RCR_CBSSID_DATA // Accept BSSID match packet
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#define RCR_APWRMGT (1 << 5) // Accept power management packet
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#define RCR_ADD3 (1 << 4) // Accept address 3 match packet
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#define RCR_AB (1 << 3) // Accept broadcast packet
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|
#define RCR_AM (1 << 2) // Accept multicast packet
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|
#define RCR_APM (1 << 1) // Accept physical match packet
|
|
#define RCR_AAP (1 << 0) // Accept all unicast packet
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|
|
|
#define AAP (1 << 0)
|
|
#define APM (1 << 1)
|
|
#define AM (1 << 2)
|
|
#define AB (1 << 3)
|
|
#define ADD3 (1 << 4)
|
|
#define APWRMGT (1 << 5)
|
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#define CBSSID (1 << 6)
|
|
#define CBSSID_DATA (1 << 6)
|
|
#define CBSSID_BCN (1 << 7)
|
|
#define ACRC32 (1 << 8)
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|
#define AICV (1 << 9)
|
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#define ADF (1 << 11)
|
|
#define ACF (1 << 12)
|
|
#define AMF (1 << 13)
|
|
#define HTC_LOC_CTRL (1 << 14)
|
|
#define UC_DATA_EN (1 << 16)
|
|
#define BM_DATA_EN (1 << 17)
|
|
#define MFBEN (1 << 22)
|
|
#define LSIGEN (1 << 23)
|
|
#define EnMBID (1 << 24)
|
|
#define APP_BASSN (1 << 27)
|
|
#define APP_PHYSTS (1 << 28)
|
|
#define APP_ICV (1 << 29)
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#define APP_MIC (1 << 30)
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|
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/* 8711 CAM Config Setting (offset 0x680, 1 byte) */
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#define SCR_TxUseDK (1 << 0) // Force Tx Use Default Key
|
|
#define SCR_RxUseDK (1 << 1) // Force Rx Use Default Key
|
|
#define SCR_TxEncEnable (1 << 2) // Enable Tx Encryption
|
|
#define SCR_RxDecEnable (1 << 3) // Enable Rx Decryption
|
|
#define SCR_SKByA2 (1 << 4) // Search kEY BY A2
|
|
#define SCR_NoSKMC (1 << 5) // No Key Search Multicast
|
|
#define SCR_TXBCUSEDK (1 << 6) // Force Tx Broadcast packets Use Default Key
|
|
#define SCR_RXBCUSEDK (1 << 7) // Force Rx Broadcast packets Use Default Key
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|
|
#define CAM_NONE 0x0
|
|
#define CAM_WEP40 0x01
|
|
#define CAM_TKIP 0x02
|
|
#define CAM_AES 0x04
|
|
#define CAM_WEP104 0x05
|
|
#define CAM_SMS4 0x6
|
|
|
|
#define TOTAL_CAM_ENTRY 32
|
|
#define HALF_CAM_ENTRY 16
|
|
|
|
#define CAM_CONFIG_USEDK TRUE
|
|
#define CAM_CONFIG_NO_USEDK FALSE
|
|
|
|
#define SCR_UseDK 0x01
|
|
#define SCR_TxSecEnable 0x02
|
|
#define SCR_RxSecEnable 0x04
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|
|
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/* 8711 REG_BCN_PSR_RPT (Beacon Parser Report Register) (Offset 0x6A8, 32 bits)
|
|
*/
|
|
#define PS_TIM (1 << 14)
|
|
#define PS_DTIM (1 << 15)
|
|
|
|
#endif
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